[PATCH v3 3/8] LoongArch: Prepare for assemblers with proper FCSR class support

From: WANG Xuerui
Date: Sun Jun 25 2023 - 05:57:13 EST


From: WANG Xuerui <git@xxxxxxxxxx>

The GNU assembler (as of 2.40) mis-treats FCSR operands as GPRs, but
the LLVM IAS does not. Probe for this and refer to FCSRs as "$fcsrNN"
if support is present.

Signed-off-by: WANG Xuerui <git@xxxxxxxxxx>
---
arch/loongarch/Kconfig | 3 +++
arch/loongarch/include/asm/fpregdef.h | 7 +++++++
arch/loongarch/include/asm/loongarch.h | 9 ++++++++-
3 files changed, 18 insertions(+), 1 deletion(-)

diff --git a/arch/loongarch/Kconfig b/arch/loongarch/Kconfig
index 743d87655742..ac3564935281 100644
--- a/arch/loongarch/Kconfig
+++ b/arch/loongarch/Kconfig
@@ -242,6 +242,9 @@ config SCHED_OMIT_FRAME_POINTER
config AS_HAS_EXPLICIT_RELOCS
def_bool $(as-instr,x:pcalau12i \$t0$(comma)%pc_hi20(x))

+config AS_HAS_FCSR_CLASS
+ def_bool $(as-instr,x:movfcsr2gr \$t0$(comma)\$fcsr0)
+
config CC_HAS_LSX_EXTENSION
def_bool $(cc-option,-mlsx)

diff --git a/arch/loongarch/include/asm/fpregdef.h b/arch/loongarch/include/asm/fpregdef.h
index b6be527831dd..3eb7ff9e1d8e 100644
--- a/arch/loongarch/include/asm/fpregdef.h
+++ b/arch/loongarch/include/asm/fpregdef.h
@@ -40,6 +40,12 @@
#define fs6 $f30
#define fs7 $f31

+#ifdef CONFIG_AS_HAS_FCSR_CLASS
+#define fcsr0 $fcsr0
+#define fcsr1 $fcsr1
+#define fcsr2 $fcsr2
+#define fcsr3 $fcsr3
+#else
/*
* Current binutils expects *GPRs* at FCSR position for the FCSR
* operation instructions, so define aliases for those used.
@@ -48,5 +54,6 @@
#define fcsr1 $r1
#define fcsr2 $r2
#define fcsr3 $r3
+#endif

#endif /* _ASM_FPREGDEF_H */
diff --git a/arch/loongarch/include/asm/loongarch.h b/arch/loongarch/include/asm/loongarch.h
index ac83e60c60d1..ff4482fd8ad7 100644
--- a/arch/loongarch/include/asm/loongarch.h
+++ b/arch/loongarch/include/asm/loongarch.h
@@ -1445,11 +1445,18 @@ __BUILD_CSR_OP(tlbidx)
#define EXCCODE_INT_START 64
#define EXCCODE_INT_END (EXCCODE_INT_START + EXCCODE_INT_NUM - 1)

-/* FPU register names */
+/* FPU Status Register Names */
+#ifdef CONFIG_AS_HAS_FCSR_CLASS
+#define LOONGARCH_FCSR0 $fcsr0
+#define LOONGARCH_FCSR1 $fcsr1
+#define LOONGARCH_FCSR2 $fcsr2
+#define LOONGARCH_FCSR3 $fcsr3
+#else
#define LOONGARCH_FCSR0 $r0
#define LOONGARCH_FCSR1 $r1
#define LOONGARCH_FCSR2 $r2
#define LOONGARCH_FCSR3 $r3
+#endif

/* FPU Status Register Values */
#define FPU_CSR_RSVD 0xe0e0fce0
--
2.40.0