Re: [PATCH v3 2/6] drm/msm/a6xx: Use descriptive bitfield names for CP_PROTECT_CNTL
From: kernel test robot
Date: Tue Jun 20 2023 - 03:20:11 EST
Hi Konrad,
kernel test robot noticed the following build errors:
[auto build test ERROR on 47045630bc409ce6606d97b790895210dd1d517d]
url: https://github.com/intel-lab-lkp/linux/commits/Konrad-Dybcio/drm-msm-a6xx-Add-some-missing-header-definitions/20230620-004639
base: 47045630bc409ce6606d97b790895210dd1d517d
patch link: https://lore.kernel.org/r/20230517-topic-a7xx_prep-v3-2-a3ce3725385b%40linaro.org
patch subject: [PATCH v3 2/6] drm/msm/a6xx: Use descriptive bitfield names for CP_PROTECT_CNTL
config: arm-allmodconfig (https://download.01.org/0day-ci/archive/20230620/202306201502.pisn6tpR-lkp@xxxxxxxxx/config)
compiler: arm-linux-gnueabi-gcc (GCC) 12.3.0
reproduce: (https://download.01.org/0day-ci/archive/20230620/202306201502.pisn6tpR-lkp@xxxxxxxxx/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@xxxxxxxxx>
| Closes: https://lore.kernel.org/oe-kbuild-all/202306201502.pisn6tpR-lkp@xxxxxxxxx/
All errors (new ones prefixed by >>):
drivers/gpu/drm/msm/adreno/a6xx_gpu.c: In function 'a6xx_set_cp_protect':
>> drivers/gpu/drm/msm/adreno/a6xx_gpu.c:934:19: error: 'A6XX_CP_PROTECT_CNTL_ACCESS_PROT_EN' undeclared (first use in this function)
934 | A6XX_CP_PROTECT_CNTL_ACCESS_PROT_EN |
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/msm/adreno/a6xx_gpu.c:934:19: note: each undeclared identifier is reported only once for each function it appears in
>> drivers/gpu/drm/msm/adreno/a6xx_gpu.c:935:19: error: 'A6XX_CP_PROTECT_CNTL_ACCESS_FAULT_ON_VIOL_EN' undeclared (first use in this function)
935 | A6XX_CP_PROTECT_CNTL_ACCESS_FAULT_ON_VIOL_EN |
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>> drivers/gpu/drm/msm/adreno/a6xx_gpu.c:936:19: error: 'A6XX_CP_PROTECT_CNTL_LAST_SPAN_INF_RANGE' undeclared (first use in this function)
936 | A6XX_CP_PROTECT_CNTL_LAST_SPAN_INF_RANGE);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Kconfig warnings: (for reference only)
WARNING: unmet direct dependencies detected for SM_GCC_8350
Depends on [n]: COMMON_CLK [=y] && COMMON_CLK_QCOM [=m] && (ARM64 || COMPILE_TEST [=n])
Selected by [m]:
- SM_VIDEOCC_8350 [=m] && COMMON_CLK [=y] && COMMON_CLK_QCOM [=m]
WARNING: unmet direct dependencies detected for SM_GCC_8450
Depends on [n]: COMMON_CLK [=y] && COMMON_CLK_QCOM [=m] && (ARM64 || COMPILE_TEST [=n])
Selected by [m]:
- SM_GPUCC_8450 [=m] && COMMON_CLK [=y] && COMMON_CLK_QCOM [=m]
- SM_VIDEOCC_8450 [=m] && COMMON_CLK [=y] && COMMON_CLK_QCOM [=m]
WARNING: unmet direct dependencies detected for SM_GCC_8550
Depends on [n]: COMMON_CLK [=y] && COMMON_CLK_QCOM [=m] && (ARM64 || COMPILE_TEST [=n])
Selected by [m]:
- SM_GPUCC_8550 [=m] && COMMON_CLK [=y] && COMMON_CLK_QCOM [=m]
- SM_VIDEOCC_8550 [=m] && COMMON_CLK [=y] && COMMON_CLK_QCOM [=m]
vim +/A6XX_CP_PROTECT_CNTL_ACCESS_PROT_EN +934 drivers/gpu/drm/msm/adreno/a6xx_gpu.c
899
900 static void a6xx_set_cp_protect(struct msm_gpu *gpu)
901 {
902 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
903 const u32 *regs = a6xx_protect;
904 unsigned i, count, count_max;
905
906 if (adreno_is_a650(adreno_gpu)) {
907 regs = a650_protect;
908 count = ARRAY_SIZE(a650_protect);
909 count_max = 48;
910 BUILD_BUG_ON(ARRAY_SIZE(a650_protect) > 48);
911 } else if (adreno_is_a690(adreno_gpu)) {
912 regs = a690_protect;
913 count = ARRAY_SIZE(a690_protect);
914 count_max = 48;
915 BUILD_BUG_ON(ARRAY_SIZE(a690_protect) > 48);
916 } else if (adreno_is_a660_family(adreno_gpu)) {
917 regs = a660_protect;
918 count = ARRAY_SIZE(a660_protect);
919 count_max = 48;
920 BUILD_BUG_ON(ARRAY_SIZE(a660_protect) > 48);
921 } else {
922 regs = a6xx_protect;
923 count = ARRAY_SIZE(a6xx_protect);
924 count_max = 32;
925 BUILD_BUG_ON(ARRAY_SIZE(a6xx_protect) > 32);
926 }
927
928 /*
929 * Enable access protection to privileged registers, fault on an access
930 * protect violation and select the last span to protect from the start
931 * address all the way to the end of the register address space
932 */
933 gpu_write(gpu, REG_A6XX_CP_PROTECT_CNTL,
> 934 A6XX_CP_PROTECT_CNTL_ACCESS_PROT_EN |
> 935 A6XX_CP_PROTECT_CNTL_ACCESS_FAULT_ON_VIOL_EN |
> 936 A6XX_CP_PROTECT_CNTL_LAST_SPAN_INF_RANGE);
937
938 for (i = 0; i < count - 1; i++)
939 gpu_write(gpu, REG_A6XX_CP_PROTECT(i), regs[i]);
940 /* last CP_PROTECT to have "infinite" length on the last entry */
941 gpu_write(gpu, REG_A6XX_CP_PROTECT(count_max - 1), regs[i]);
942 }
943
--
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