Re: [PATCH v3 2/9] clk: ralink: add clock and reset driver for MTMIPS SoCs

[Sergio Paracuellos]

Hi Krzysztof,

On Sat, Jun 17, 2023 at 3:07 PM Krzysztof Kozlowski
<krzysztof.kozlowski@xxxxxxxxxx> wrote:
>
> On 17/06/2023 14:54, Shiji Yang wrote:
> >> void __init plat_time_init(void)
> >> {
> >> +    struct of_phandle_args clkspec;
> >>      struct clk *clk;
> >> +    int cpu_clk_idx;
> >>
> >>      ralink_of_remap();
> >>
> >> -    ralink_clk_init();
> >> -    clk = clk_get_sys("cpu", NULL);
> >> +    cpu_clk_idx = clk_cpu_index();
> >> +    if (cpu_clk_idx == -1)
> >> +            panic("unable to get CPU clock index");
> >> +
> >> +    of_clk_init(NULL);
> >> +    clkspec.np = of_find_node_by_name(NULL, "sysc");
> >
> > The node name should be "syscon" as the example node name in the
> > dt-bindings document is "syscon".
>
> NAK for both.
>
> Node names must not be an ABI, unless you talk about child of some
> device node. I don't think this is the case here. Look by phandle (for a
> device context) or by compatible (looks the case here).

We need to get the cpu clock to set the initial cpu clock here. Search
by 'sysc' is the only  shared in all the dtsi files since it is the
clock provider node. Why is this not correct? I don't understand what
you mean with look by phandle for a device context. The case of
searching for compatible is a mess since as you can see in the
bindings there are tons of compatibles to search for, then (this code
is common to all ralink platforms).

Thanks in advance for clarification.

Best regards,
    Sergio Paracuellos
>
>
>
> Best regards,
> Krzysztof
>