Re: [PATCH v3 2/9] clk: ralink: add clock and reset driver for MTMIPS SoCs

[Stephen Boyd]

Quoting Sergio Paracuellos (2023-04-18 02:03:05)
> Until now, clock related code for old ralink SoCs was based in fixed clocks
> using 'clk_register_fixed_rate' and 'clkdev_create' directly doing in code
> and not using device tree at all for their definition. Including this driver
> is an effort to be able to define proper clocks using device tree and also
> cleaning all the clock and reset related code from 'arch/mips/ralink' dir.
> This clock and reset driver covers all the ralink SoCs but MT7621 which is
> the newest and provides gating and some differences that make it different
> from its predecesors. It has its own driver since some time ago. The ralink
> SoCs we are taking about are RT2880, RT3050, RT3052, RT3350, RT3352, RT3883,
> RT5350, MT7620, MT7628 and MT7688. Mostly the code in this new driver has
> been extracted from 'arch/mips/ralink' and cleanly put using kernel clock
> driver APIs. The clock plans for this SoCs only talks about relation between
> CPU frequency and BUS frequency. This relation is different depending on the
> particular SoC. CPU clock is derived from XTAL frequencies.
> 
> Depending on the SoC we have the following frequencies:
> * RT2880 SoC:
>     - XTAL: 40 MHz.
>     - CPU: 250, 266, 280 or 300 MHz.
>     - BUS: CPU / 2 MHz.
> * RT3050, RT3052, RT3350:
>     - XTAL: 40 MHz.
>     - CPU: 320 or 384 MHz.
>     - BUS: CPU / 3 MHz.
> * RT3352:
>     - XTAL: 40 MHz.
>     - CPU: 384 or 400 MHz.
>     - BUS: CPU / 3 MHz.
>     - PERIPH: 40 MHz.
> * RT3383:
>     - XTAL: 40 MHz.
>     - CPU: 250, 384, 480 or 500 MHz.
>     - BUS: Depends on RAM Type and CPU:
>         + RAM DDR2: 125. ELSE 83 MHz.
>         + RAM DDR2: 128. ELSE 96 MHz.
>         + RAM DDR2: 160. ELSE 120 MHz.
>         + RAM DDR2: 166. ELSE 125 MHz.
> * RT5350:
>     - XTAL: 40 MHz.
>     - CPU: 300, 320 or 360 MHz.
>     - BUS: CPU / 3, CPU / 4, CPU / 3 MHz.
>     - PERIPH: 40 MHz.
> * MT7628 and MT7688:
>     - XTAL: 20 MHz or 40 MHz.
>     - CPU: 575 or 580 MHz.
>     - BUS: CPU / 3.
>     - PCMI2S: 480 MHz.
>     - PERIPH: 40 MHz.
> * MT7620:
>     - XTAL: 20 MHz or 40 MHz.
>     - PLL: XTAL, 480, 600 MHz.
>     - CPU: depends on PLL and some mult and dividers.
>     - BUS: depends on PLL and some mult and dividers.
>     - PERIPH: 40 or XTAL MHz.
> 
> MT7620 is a bit more complex deriving CPU clock from a PLL and an bunch of
> register reads and predividers. To derive CPU and BUS frequencies in the
> MT7620 SoC 'mt7620_calc_rate()' helper is used.
> 
> In the case XTAL can have different frequencies and we need a different
> clock frequency for peripherals 'periph' clock in introduced.
> 
> The rest of the peripherals present in the SoC just follow their parent
> frequencies.
> 
> With this information the clk driver will provide all the clock and reset
> functionality from a set of hardcoded clocks allowing to define a nice
> device tree without fixed clocks.
> 
> Signed-off-by: Sergio Paracuellos <sergio.paracuellos@xxxxxxxxx>
> ---

Acked-by: Stephen Boyd <sboyd@xxxxxxxxxx>