Re: [PATCH 3/3] dt-bindings: riscv: sifive: Add SiFive Private L2 cache controller

From: Ben Dooks
Date: Fri Jun 16 2023 - 07:07:34 EST


On 16/06/2023 11:10, Conor Dooley wrote:
Hey Eric,

On Fri, Jun 16, 2023 at 02:32:10PM +0800, Eric Lin wrote:
This add YAML DT binding documentation for SiFive Private L2
cache controller

Signed-off-by: Eric Lin <eric.lin@xxxxxxxxxx>
Reviewed-by: Zong Li <zong.li@xxxxxxxxxx>
Reviewed-by: Nick Hu <nick.hu@xxxxxxxxxx>

Firstly, bindings need to come before the driver using them.

---
.../bindings/riscv/sifive,pL2Cache0.yaml | 81 +++++++++++++++++++
1 file changed, 81 insertions(+)
create mode 100644 Documentation/devicetree/bindings/riscv/sifive,pL2Cache0.yaml

diff --git a/Documentation/devicetree/bindings/riscv/sifive,pL2Cache0.yaml b/Documentation/devicetree/bindings/riscv/sifive,pL2Cache0.yaml
new file mode 100644
index 000000000000..b5d8d4a39dde
--- /dev/null
+++ b/Documentation/devicetree/bindings/riscv/sifive,pL2Cache0.yaml

Cache bindings have moved to devicetree/bindings/cache.

@@ -0,0 +1,81 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+# Copyright (C) 2023 SiFive, Inc.
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/riscv/sifive,pL2Cache0.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: SiFive Private L2 Cache Controller
+
+maintainers:
+ - Greentime Hu <greentime.hu@xxxxxxxxxx>
+ - Eric Lin <eric.lin@xxxxxxxxxx>

Drop the alignment here please.

+
+description:
+ The SiFive Private L2 Cache Controller is per hart and communicates with both the upstream
+ L1 caches and downstream L3 cache or memory, enabling a high-performance cache subsystem.
+ All the properties in ePAPR/DeviceTree specification applies for this platform.

Please wrap before 80 characters.

+
+allOf:
+ - $ref: /schemas/cache-controller.yaml#
+
+select:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - sifive,pL2Cache0
+ - sifive,pL2Cache1

Why is this select: required?

+ required:
+ - compatible
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - sifive,pL2Cache0
+ - sifive,pL2Cache1

What is the difference between these? (and drop the caps please)

Should this also not fall back to "cache"?

I thought cache is required as the last resort.
Ben Dooks http://www.codethink.co.uk/
Senior Engineer Codethink - Providing Genius

https://www.codethink.co.uk/privacy.html