Re: [PATCH 2/2] spi: spi-geni-qcom: Add SPI SLAVE mode support for GENI based QuPv3

[Praveen Talari]

Hi

Thank you for review.

On 6/13/2023 1:12 PM, Shazad Hussain wrote:
> On 6/13/2023 12:22 PM, Praveen Talari wrote:
> > Add SPI SLAVE mode support for GENI based QuPv3.
> >
> > Signed-off-by: Praveen Talari <quic_ptalari@xxxxxxxxxxx>
> > ---
> >   drivers/spi/spi-geni-qcom.c | 55 +++++++++++++++++++++++++++++++++----
> >   1 file changed, 49 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/spi/spi-geni-qcom.c b/drivers/spi/spi-geni-qcom.c
> > index 206cc04bb1ed..2e3ae29e79e0 100644
> > --- a/drivers/spi/spi-geni-qcom.c
> > +++ b/drivers/spi/spi-geni-qcom.c
> > @@ -12,6 +12,7 @@
> >   #include <linux/platform_device.h>
> >   #include <linux/pm_opp.h>
> >   #include <linux/pm_runtime.h>
> > +#include <linux/property.h>
> >   #include <linux/soc/qcom/geni-se.h>
> >   #include <linux/spi/spi.h>
> >   #include <linux/spinlock.h>
> > @@ -52,6 +53,9 @@
> >   #define SPI_CS_CLK_DELAY_MSK        GENMASK(19, 10)
> >   #define SPI_CS_CLK_DELAY_SHFT        10
> >   +#define SE_SPI_SLAVE_EN                (0x2BC)
> > +#define SPI_SLAVE_EN                BIT(0)
> > +
> >   /* M_CMD OP codes for SPI */
> >   #define SPI_TX_ONLY        1
> >   #define SPI_RX_ONLY        2
> > @@ -99,6 +103,24 @@ struct spi_geni_master {
> >       int cur_xfer_mode;
> >   };
> >   +static struct spi_master *get_spi_master(struct device *dev)
> > +{
> > +    struct platform_device *pdev = to_platform_device(dev);
> > +    struct spi_master *spi = platform_get_drvdata(pdev);
> > +
> > +    return spi;
> > +}
> > +
> > +static void spi_slv_setup(struct spi_geni_master *mas)
> > +{
> > +    struct geni_se *se = &mas->se;
> > +
> > +    writel(SPI_SLAVE_EN, se->base + SE_SPI_SLAVE_EN);
> > +    writel(GENI_IO_MUX_0_EN, se->base + GENI_OUTPUT_CTRL);
> > +    writel(START_TRIGGER, se->base + SE_GENI_CFG_SEQ_START);
> > +    dev_info(mas->dev, "spi slave setup done\n");
> > +}
> > +
> >   static int get_spi_clk_cfg(unsigned int speed_hz,
> >               struct spi_geni_master *mas,
> >               unsigned int *clk_idx,
> > @@ -140,12 +162,18 @@ static void handle_se_timeout(struct spi_master 
> > *spi,
> >       const struct spi_transfer *xfer;
> >         spin_lock_irq(&mas->lock);
> > -    reinit_completion(&mas->cancel_done);
> >       if (mas->cur_xfer_mode == GENI_SE_FIFO)
> >           writel(0, se->base + SE_GENI_TX_WATERMARK_REG);
> >         xfer = mas->cur_xfer;
> >       mas->cur_xfer = NULL;
> > +
> > +    if (spi->slave) {
> > +        spin_unlock_irq(&mas->lock);
> > +        goto unmap_if_dma;
> > +    }
> > +
> > +    reinit_completion(&mas->cancel_done);
> >       geni_se_cancel_m_cmd(se);
> >       spin_unlock_irq(&mas->lock);
> >   @@ -541,6 +569,8 @@ static bool geni_can_dma(struct spi_controller 
> > *ctlr,
> >         if (mas->cur_xfer_mode == GENI_GPI_DMA)
> >           return true;
> > +    if (ctlr->slave)
> > +        return true;
> >         len = get_xfer_len_in_words(xfer, mas);
> >       fifo_size = mas->tx_fifo_depth * mas->fifo_width_bits / 
> > mas->cur_bits_per_word;
> > @@ -619,6 +649,7 @@ static void spi_geni_release_dma_chan(struct 
> > spi_geni_master *mas)
> >     static int spi_geni_init(struct spi_geni_master *mas)
> >   {
> > +    struct spi_master *spi = get_spi_master(mas->dev);
> >       struct geni_se *se = &mas->se;
> >       unsigned int proto, major, minor, ver;
> >       u32 spi_tx_cfg, fifo_disable;
> > @@ -627,7 +658,14 @@ static int spi_geni_init(struct spi_geni_master 
> > *mas)
> >       pm_runtime_get_sync(mas->dev);
> >         proto = geni_se_read_proto(se);
> > -    if (proto != GENI_SE_SPI) {
> > +
> > +    if (spi->slave) {
> > +        if (proto != GENI_SE_SPI_SLAVE) {
> > +            dev_err(mas->dev, "Invalid proto %d\n", proto);
> > +            goto out_pm;
> > +        }
> > +        spi_slv_setup(mas);
> > +    } else if (proto != GENI_SE_SPI) {
> >           dev_err(mas->dev, "Invalid proto %d\n", proto);
> >           goto out_pm;
> >       }
> > @@ -677,9 +715,11 @@ static int spi_geni_init(struct spi_geni_master 
> > *mas)
> >       }
> >         /* We always control CS manually */
> > -    spi_tx_cfg = readl(se->base + SE_SPI_TRANS_CFG);
> > -    spi_tx_cfg &= ~CS_TOGGLE;
> > -    writel(spi_tx_cfg, se->base + SE_SPI_TRANS_CFG);
> > +    if (!spi->slave) {
> > +        spi_tx_cfg = readl(se->base + SE_SPI_TRANS_CFG);
> > +        spi_tx_cfg &= ~CS_TOGGLE;
> > +        writel(spi_tx_cfg, se->base + SE_SPI_TRANS_CFG);
> > +    }
> >     out_pm:
> >       pm_runtime_put(mas->dev);
> > @@ -1072,6 +1112,9 @@ static int spi_geni_probe(struct 
> > platform_device *pdev)
> >       pm_runtime_set_autosuspend_delay(&pdev->dev, 250);
> >       pm_runtime_enable(dev);
> >   +    if (device_property_read_bool(&pdev->dev, "qcom,slv-ctrl"))
>
> Should we update this property "qcom,slv-ctrl" in device tree bindings
> as well !!
Done
> > +        spi->slave = true;
> > +
> >       ret = geni_icc_get(&mas->se, NULL);
> >       if (ret)
> >           goto spi_geni_probe_runtime_disable;
> > @@ -1092,7 +1135,7 @@ static int spi_geni_probe(struct 
> > platform_device *pdev)
> >        * for dma (gsi) mode, the gsi will set cs based on params 
> > passed in
> >        * TRE
> >        */
> > -    if (mas->cur_xfer_mode == GENI_SE_FIFO)
> > +    if (!spi->slave && mas->cur_xfer_mode == GENI_SE_FIFO)
> >           spi->set_cs = spi_geni_set_cs;
> >         ret = request_irq(mas->irq, geni_spi_isr, 0, dev_name(dev), 
> > spi);
>
> -Shazad