Re: [PATCH 4/9] drm: atmel-hlcdc: Define SAM9X7 XLCDC specific registers

From: Manikandan.M
Date: Thu Jun 15 2023 - 01:28:20 EST

On 14/06/23 12:17, Claudiu Beznea - M18063 wrote:
> Hi, Manikandan,
>
> On 13.06.2023 10:04, Manikandan Muralidharan wrote:
>> From: Durai Manickam KR <durai.manickamkr@xxxxxxxxxxxxx>
>>
>> The register address of the XLCDC IP used in SAM9X7 are different from
>> the previous HLCDC.Defining those address space with valid macros.
>>
>> Signed-off-by: Durai Manickam KR <durai.manickamkr@xxxxxxxxxxxxx>
>> [manikandan.m@xxxxxxxxxxxxx: Remove unused macro definitions]
>> Signed-off-by: Manikandan Muralidharan <manikandan.m@xxxxxxxxxxxxx>
>> ---
>> drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h | 108 +++++++++++++++++++
>> include/linux/mfd/atmel-hlcdc.h | 10 ++
>> 2 files changed, 118 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h
>> index 5b5c774e0edf..aed1742b3665 100644
>> --- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h
>> +++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h
>> @@ -15,6 +15,7 @@
>>
>> #include <drm/drm_plane.h>
>>
>> +/* LCD controller common registers */
>> #define ATMEL_HLCDC_LAYER_CHER 0x0
>> #define ATMEL_HLCDC_LAYER_CHDR 0x4
>> #define ATMEL_HLCDC_LAYER_CHSR 0x8
>> @@ -128,6 +129,113 @@
>>
>> #define ATMEL_HLCDC_MAX_LAYERS 6
>>
>> +/* XLCDC controller specific registers */
>> +#define ATMEL_XLCDC_LAYER_ENR 0x10
>> +#define ATMEL_XLCDC_LAYER_EN BIT(0)
>> +
>> +#define ATMEL_XLCDC_LAYER_IER 0x0
>> +#define ATMEL_XLCDC_LAYER_IDR 0x4
>> +#define ATMEL_XLCDC_LAYER_IMR 0x8
>> +#define ATMEL_XLCDC_LAYER_ISR 0xc
>> +#define ATMEL_XLCDC_LAYER_DONE_IRQ(p) BIT(0 + (8 * (p)))
>> +#define ATMEL_XLCDC_LAYER_ERROR_IRQ(p) BIT(1 + (8 * (p)))
>> +#define ATMEL_XLCDC_LAYER_OVR_IRQ(p) BIT(2 + (8 * (p)))
>> +
>> +#define ATMEL_XLCDC_LAYER_PLANE_ADDR(p) (((p) * 0x4) + 0x18)
>> +
>> +#define ATMEL_XLCDC_LAYER_DMA_CFG 0
>> +#define ATMEL_XLCDC_LAYER_DMA_BLEN_MASK GENMASK(6, 4)
>> +#define ATMEL_XLCDC_LAYER_DMA_BLEN_SINGLE (0 << 4)
>> +#define ATMEL_XLCDC_LAYER_DMA_BLEN_INCR32 (4 << 4)
>> +#define ATMEL_XLCDC_LAYER_DMA_BLENCC_MASK GENMASK(10, 8)
>> +#define ATMEL_XLCDC_LAYER_DMA_BLENCC_SINGLE (0 << 8)
>> +#define ATMEL_XLCDC_LAYER_DMA_BLENCC_INCR4 (1 << 8)
>> +#define ATMEL_XLCDC_LAYER_DMA_BLENCC_INCR8 (2 << 8)
>> +#define ATMEL_XLCDC_LAYER_DMA_BLENCC_INCR16 (3 << 8)
>> +#define ATMEL_XLCDC_LAYER_DMA_BLENCC_INCR32 (4 << 8)
>> +
>> +#define ATMEL_XLCDC_GAM BIT(2)
>> +
>> +#define ATMEL_XLCDC_LAYER_POS(x, y) ((x) | ((y) << 16))
>> +#define ATMEL_XLCDC_LAYER_SIZE(w, h) (((w) - 1) | (((h) - 1) << 16))
>> +
>> +#define ATMEL_XLCDC_LAYER_DMA BIT(0)
>> +#define ATMEL_XLCDC_LAYER_REP BIT(1)
>> +#define ATMEL_XLCDC_LAYER_CRKEY BIT(2)
>> +#define ATMEL_XLCDC_LAYER_DSTKEY BIT(3)
>> +#define ATMEL_XLCDC_LAYER_DISCEN BIT(4)
>> +#define ATMEL_XLCDC_LAYER_VIDPRI BIT(5)
>> +#define ATMEL_XLCDC_LAYER_SFACTC_MASK GENMASK(8, 6)
>> +#define ATMEL_XLCDC_LAYER_SFACTC_ONE (0 << 6)
>> +#define ATMEL_XLCDC_LAYER_SFACTC_ZERO (1 << 6)
>> +#define ATMEL_XLCDC_LAYER_SFACTC_A0 (2 << 6)
>> +#define ATMEL_XLCDC_LAYER_SFACTC_A0_MULT_AD (3 << 6)
>> +#define ATMEL_XLCDC_LAYER_SFACTC_A0_MULT_AS (4 << 6)
>> +#define ATMEL_XLCDC_LAYER_SFACTC_M_A0_MULT_AD (5 << 6)
>> +#define ATMEL_XLCDC_LAYER_SFACTA_MASK GENMASK(10, 9)
>> +#define ATMEL_XLCDC_LAYER_SFACTA_ZERO (0 << 9)
>> +#define ATMEL_XLCDC_LAYER_SFACTA_ONE (1 << 9)
>> +#define ATMEL_XLCDC_LAYER_SFACTA_A0 (2 << 9)
>> +#define ATMEL_XLCDC_LAYER_SFACTA_A1 (3 << 9)
>> +#define ATMEL_XLCDC_LAYER_DFACTC_MASK GENMASK(13, 11)
>> +#define ATMEL_XLCDC_LAYER_DFACTC_ZERO (0 << 11)
>> +#define ATMEL_XLCDC_LAYER_DFACTC_ONE (1 << 11)
>> +#define ATMEL_XLCDC_LAYER_DFACTC_A0 (2 << 11)
>> +#define ATMEL_XLCDC_LAYER_DFACTC_A1 (3 << 11)
>> +#define ATMEL_XLCDC_LAYER_DFACTC_A0_MULT_AD (4 << 11)
>> +#define ATMEL_XLCDC_LAYER_DFACTC_M_A0_MULT_AD (5 << 11)
>> +#define ATMEL_XLCDC_LAYER_DFACTC_M_A0_MULT_AS (6 << 11)
>> +#define ATMEL_XLCDC_LAYER_DFACTC_M_A0 (7 << 11)
>> +#define ATMEL_XLCDC_LAYER_DFACTA_MASK GENMASK(15, 14)
>> +#define ATMEL_XLCDC_LAYER_DFACTA_ZERO (0 << 14)
>> +#define ATMEL_XLCDC_LAYER_DFACTA_ONE (1 << 14)
>> +#define ATMEL_XLCDC_LAYER_DFACTA_M_A0_MULT_AS (2 << 14)
>> +#define ATMEL_XLCDC_LAYER_DFACTA_A1 (3 << 14)
>> +#define ATMEL_XLCDC_LAYER_A0_SHIFT 16
>> +#define ATMEL_XLCDC_LAYER_A0_MASK \
>> + GENMASK(23, ATMEL_XLCDC_LAYER_A0_SHIFT)
>> +#define ATMEL_XLCDC_LAYER_A0(x) \
>> + ((x) << ATMEL_XLCDC_LAYER_A0_SHIFT)
>> +#define ATMEL_XLCDC_LAYER_A1_SHIFT 24
>> +#define ATMEL_XLCDC_LAYER_A1_MASK \
>> + GENMASK(31, ATMEL_XLCDC_LAYER_A1_SHIFT)
>> +#define ATMEL_XLCDC_LAYER_A1(x) \
>> + ((x) << ATMEL_XLCDC_LAYER_A1_SHIFT)
>> +
>> +#define ATMEL_XLCDC_LAYER_DISC_POS(x, y) ((x) | ((y) << 16))
>> +#define ATMEL_XLCDC_LAYER_DISC_SIZE(w, h) (((w) - 1) | (((h) - 1) << 16))
>> +
>> +#define ATMEL_XLCDC_LAYER_VSCALER_LUMA_ENABLE BIT(0)
>> +#define ATMEL_XLCDC_LAYER_VSCALER_CHROMA_ENABLE BIT(1)
>> +#define ATMEL_XLCDC_LAYER_HSCALER_LUMA_ENABLE BIT(4)
>> +#define ATMEL_XLCDC_LAYER_HSCALER_CHROMA_ENABLE BIT(5)
>> +
>> +#define ATMEL_XLCDC_LAYER_VXSYCFG_ZERO (0 << 0)
>> +#define ATMEL_XLCDC_LAYER_VXSYCFG_ONE (1 << 0)
>> +#define ATMEL_XLCDC_LAYER_VXSYCFG_TWO (2 << 0)
>> +#define ATMEL_XLCDC_LAYER_VXSYCFG_THREE (3 << 0)
>> +#define ATMEL_XLCDC_LAYER_VXSYTAP2_ENABLE BIT(4)
>> +#define ATMEL_XLCDC_LAYER_VXSYBICU_ENABLE BIT(5)
>> +#define ATMEL_XLCDC_LAYER_VXSCCFG_ZERO (0 << 16)
>> +#define ATMEL_XLCDC_LAYER_VXSCCFG_ONE (1 << 16)
>> +#define ATMEL_XLCDC_LAYER_VXSCCFG_TWO (2 << 16)
>> +#define ATMEL_XLCDC_LAYER_VXSCCFG_THREE (3 << 16)
>> +#define ATMEL_XLCDC_LAYER_VXSCTAP2_ENABLE BIT(20)
>> +#define ATMEL_XLCDC_LAYER_VXSCBICU_ENABLE BIT(21)
>> +
>> +#define ATMEL_XLCDC_LAYER_HXSYCFG_ZERO (0 << 0)
>> +#define ATMEL_XLCDC_LAYER_HXSYCFG_ONE (1 << 0)
>> +#define ATMEL_XLCDC_LAYER_HXSYCFG_TWO (2 << 0)
>> +#define ATMEL_XLCDC_LAYER_HXSYCFG_THREE (3 << 0)
>> +#define ATMEL_XLCDC_LAYER_HXSYTAP2_ENABLE BIT(4)
>> +#define ATMEL_XLCDC_LAYER_HXSYBICU_ENABLE BIT(5)
>> +#define ATMEL_XLCDC_LAYER_HXSCCFG_ZERO (0 << 16)
>> +#define ATMEL_XLCDC_LAYER_HXSCCFG_ONE (1 << 16)
>> +#define ATMEL_XLCDC_LAYER_HXSCCFG_TWO (2 << 16)
>> +#define ATMEL_XLCDC_LAYER_HXSCCFG_THREE (3 << 16)
>> +#define ATMEL_XLCDC_LAYER_HXSCTAP2_ENABLE BIT(20)
>> +#define ATMEL_XLCDC_LAYER_HXSCBICU_ENABLE BIT(21)
>> +
>
> There are a bunch of defines included in this file not used anywhere in the
> driver. Please check and keep only necessary.
They were defined as mentioned in the datasheet for future use.I will
remove those that are not used for XLCDC driver code.
>
> Thank you,
> Claudiu
>
>> /**
>> * Atmel HLCDC Layer registers layout structure
>> *
>> diff --git a/include/linux/mfd/atmel-hlcdc.h b/include/linux/mfd/atmel-hlcdc.h
>> index a186119a49b5..80d675a03b39 100644
>> --- a/include/linux/mfd/atmel-hlcdc.h
>> +++ b/include/linux/mfd/atmel-hlcdc.h
>> @@ -22,6 +22,8 @@
>> #define ATMEL_HLCDC_DITHER BIT(6)
>> #define ATMEL_HLCDC_DISPDLY BIT(7)
>> #define ATMEL_HLCDC_MODE_MASK GENMASK(9, 8)
>> +#define ATMEL_XLCDC_MODE_MASK GENMASK(10, 8)
>> +#define ATMEL_XLCDC_DPI BIT(11)
>> #define ATMEL_HLCDC_PP BIT(10)
>> #define ATMEL_HLCDC_VSPSU BIT(12)
>> #define ATMEL_HLCDC_VSPHO BIT(13)
>> @@ -34,6 +36,12 @@
>> #define ATMEL_HLCDC_IDR 0x30
>> #define ATMEL_HLCDC_IMR 0x34
>> #define ATMEL_HLCDC_ISR 0x38
>> +#define ATMEL_XLCDC_ATTRE 0x3c
>> +
>> +#define ATMEL_XLCDC_BASE_UPDATE BIT(0)
>> +#define ATMEL_XLCDC_OVR1_UPDATE BIT(1)
>> +#define ATMEL_XLCDC_OVR3_UPDATE BIT(2)
>> +#define ATMEL_XLCDC_HEO_UPDATE BIT(3)
>>
>> #define ATMEL_HLCDC_CLKPOL BIT(0)
>> #define ATMEL_HLCDC_CLKSEL BIT(2)
>> @@ -48,6 +56,8 @@
>> #define ATMEL_HLCDC_DISP BIT(2)
>> #define ATMEL_HLCDC_PWM BIT(3)
>> #define ATMEL_HLCDC_SIP BIT(4)
>> +#define ATMEL_XLCDC_SD BIT(5)
>> +#define ATMEL_XLCDC_CM BIT(6)
>>
>> #define ATMEL_HLCDC_SOF BIT(0)
>> #define ATMEL_HLCDC_SYNCDIS BIT(1)
>

--
Thanks and Regards,
Manikandan M.