Re: [PATCH 05/12] dt-bindings: mtd: brcmnand: Updates for bcmbca SoCs

From: William Zhang
Date: Wed Jun 14 2023 - 20:41:09 EST


Hi Rob,

On 06/14/2023 03:46 PM, Rob Herring wrote:
On Wed, Jun 07, 2023 at 10:14:52AM +0200, Miquel Raynal wrote:
Hi William,

william.zhang@xxxxxxxxxxxx wrote on Tue, 6 Jun 2023 16:12:45 -0700:

Use new compatiable brcm,nand-bcmbca to support BCMBCA broadband
product. The old compatible string is still kept in the driver so old
dtb can still work.

Add brcm,nand-use-wp property to have an option for disabling this
feature on broadband board design that does not use write protection.
Add brcm,nand-ecc-use-strap to get ecc setting from board strap for
broadband board designs because they do not specify ecc setting in dts
but rather using the strap setting.

Remove the requirement of interrupts and interrupt-names properties to
reflect the driver code.

This patch also includes a few minor fixes to the BCM63xx compatibles
and add myself to the list of maintainers.

Signed-off-by: William Zhang <william.zhang@xxxxxxxxxxxx>
---

.../bindings/mtd/brcm,brcmnand.yaml | 64 +++++++++++++------
1 file changed, 43 insertions(+), 21 deletions(-)

diff --git a/Documentation/devicetree/bindings/mtd/brcm,brcmnand.yaml b/Documentation/devicetree/bindings/mtd/brcm,brcmnand.yaml
index 1571024aa119..1fe1c166a9db 100644
--- a/Documentation/devicetree/bindings/mtd/brcm,brcmnand.yaml
+++ b/Documentation/devicetree/bindings/mtd/brcm,brcmnand.yaml
@@ -9,6 +9,7 @@ title: Broadcom STB NAND Controller
maintainers:
- Brian Norris <computersforpeace@xxxxxxxxx>
- Kamal Dasu <kdasu.kdev@xxxxxxxxx>
+ - William Zhang <william.zhang@xxxxxxxxxxxx>
description: |
The Broadcom Set-Top Box NAND controller supports low-level access to raw NAND
@@ -18,9 +19,10 @@ description: |
supports basic PROGRAM and READ functions, among other features.
This controller was originally designed for STB SoCs (BCM7xxx) but is now
- available on a variety of Broadcom SoCs, including some BCM3xxx, BCM63xx, and
- iProc/Cygnus. Its history includes several similar (but not fully register
- compatible) versions.
+ available on a variety of Broadcom SoCs, including some BCM3xxx, MIPS based
+ Broadband SoC (BCM63xx), ARM based Broadband SoC (BCMBCA) and iProc/Cygnus.
+ Its history includes several similar (but not fully register compatible)
+ versions.
-- Additional SoC-specific NAND controller properties --
@@ -53,9 +55,9 @@ properties:
- brcm,brcmnand-v7.2
- brcm,brcmnand-v7.3
- const: brcm,brcmnand
- - description: BCM63138 SoC-specific NAND controller
+ - description: BCMBCA SoC-specific NAND controller
items:
- - const: brcm,nand-bcm63138
+ - const: brcm,nand-bcmbca
- enum:
- brcm,brcmnand-v7.0
- brcm,brcmnand-v7.1
@@ -65,11 +67,15 @@ properties:
- const: brcm,nand-iproc
- const: brcm,brcmnand-v6.1
- const: brcm,brcmnand
- - description: BCM63168 SoC-specific NAND controller
+ - description: BCM63xx SoC-specific NAND controller
items:
- - const: brcm,nand-bcm63168
- - const: brcm,nand-bcm6368
- - const: brcm,brcmnand-v4.0
+ - enum:
+ - brcm,nand-bcm63168
+ - brcm,nand-bcm6368
+ - enum:
+ - brcm,brcmnand-v2.1
+ - brcm,brcmnand-v2.2
+ - brcm,brcmnand-v4.0
- const: brcm,brcmnand
reg:
@@ -111,6 +117,19 @@ properties:
earlier versions of this core that include WP
type: boolean
+ brcm,nand-use-wp:
+ description:
+ Use this integer to indicate if board design uses
+ controller's write protection feature and connects its
+ NAND_WPb pin to nand chip's WP_L pin. Driver defaults to
+ use this feature when this property does not exist.
+ Set to 0 if WP pins are not connected and feature is not
+ used. Set to 1 if WP pins are connected and feature is used.
+ Set to 2 if WP pins are connected but disable this feature
+ through driver that sets controller to output high on NAND_WPb.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 1, 2]

Perhaps strings would be welcome. I'll let binding maintainers say what
they think of it.

1 is redundant as it is the same as not present. Seems like a
'brcm,disable-wp' boolean would suffice here.
WP feature present is indicated by the existing flag brcm,nand-has-wp.
1 is the opposite of 0 (use this feature vs not use this feature while chip has this feature). 2 is kind of strange (for feature disabled intentionally at run time while feature is used), maybe for testing purpose or for certainly nand chip that has issue with WP but the board design already connect the WP pin. I keep it here to match the driver code that have these three states of the wp usage.

Rob

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