Re: [PATCH -next 3/3] clk: tegra: Fix unsigned comparison with less than zero

[Stephen Boyd]

Quoting Yang Li (2023-06-13 18:29:13)
> The return value of the round_rate() is long. However, the
> return value is being assigned to an unsigned long variable
> 'rate', so making 'rate' to long.
> 
> silence the warnings:
> ./drivers/clk/tegra/clk-periph.c:59:5-9: WARNING: Unsigned expression compared with zero: rate < 0
> ./drivers/clk/tegra/clk-super.c:156:5-9: WARNING: Unsigned expression compared with zero: rate < 0
> 
> Reported-by: Abaci Robot <abaci@xxxxxxxxxxxxxxxxx>
> Closes: https://bugzilla.openanolis.cn/show_bug.cgi?id=5519
> Signed-off-by: Yang Li <yang.lee@xxxxxxxxxxxxxxxxx>
> ---
>  drivers/clk/tegra/clk-periph.c | 2 +-
>  drivers/clk/tegra/clk-super.c  | 2 +-
>  2 files changed, 2 insertions(+), 2 deletions(-)

Instead of this can you implement determine_rate() for div_ops?