Re: [PATCH] clk: imx: composite-8m: Add imx8m_divider_determine_rate

[Maxime Ripard]

On Mon, Jun 12, 2023 at 11:11:21AM -0500, Adam Ford wrote:
> On Mon, Jun 12, 2023 at 11:08 AM Maxime Ripard <maxime@xxxxxxxxxx> wrote:
> >
> > On Sun, Jun 11, 2023 at 12:02:42PM -0500, Adam Ford wrote:
> > > On Tue, Jun 6, 2023 at 1:45 PM Fabio Estevam <festevam@xxxxxxxxx> wrote:
> > > >
> > > > On Sat, May 6, 2023 at 4:53 PM Adam Ford <aford173@xxxxxxxxx> wrote:
> > > > >
> > > > > Currently, certain clocks are derrived as a divider from their
> > > > > parent clock.  For some clocks, even when CLK_SET_RATE_PARENT
> > > > > is set, the parent clock is not properly set which can lead
> > > > > to some relatively inaccurate clock values.
> > > > >
> > >
> > > + Maxime
> > >
> > > > > Unlike imx/clk-composite-93 and imx/clk-divider-gate, it
> > > > > cannot rely on calling a standard determine_rate function,
> > > > > because the 8m composite clocks have a pre-divider and
> > > > > post-divider. Because of this, a custom determine_rate
> > > > > function is necessary to determine the maximum clock
> > > > > division which is equivalent to pre-divider * the
> > > > > post-divider.
> > > > >
> > > > > With this added, the system can attempt to adjust the parent rate
> > > > > when the proper flags are set which can lead to a more precise clock
> > > > > value.
> > > > >
> > > > > On the imx8mplus, no clock changes are present.
> > > > > On the Mini and Nano, this can help achieve more accurate
> > > > > lcdif clocks. When trying to get a pixel clock of 31.500MHz
> > > > > on an imx8m Nano, the clocks divided the 594MHz down, but
> > > > > left the parent rate untouched which caused a calulation error.
> > > > >
> > > > > Before:
> > > > > video_pll              594000000
> > > > >   video_pll_bypass     594000000
> > > > >     video_pll_out      594000000
> > > > >       disp_pixel       31263158
> > > > >         disp_pixel_clk 31263158
> > > > >
> > > > > Variance = -236842 Hz
> > > > >
> > > > > After this patch:
> > > > > video_pll               31500000
> > > > >   video_pll_bypass      31500000
> > > > >     video_pll_out       31500000
> > > > >       disp_pixel        31500000
> > > > >         disp_pixel_clk  31500000
> > > > >
> > > > > Variance = 0 Hz
> > > > >
> > > > > All other clocks rates and parent were the same.
> > > > > Similar results on imx8mm were found.
> > > > >
> > > > > Fixes: 690dccc4a0bf ("Revert "clk: imx: composite-8m: Add support to determine_rate"")
> > > > > Signed-off-by: Adam Ford <aford173@xxxxxxxxx>
> > > >
> > >
> > > Peng / Abel,
> > >
> > > Any suggestions on how we can move this forward?  Looking at the
> > > clk-composite-8m driver, imx8m_clk_composite_compute_dividers uses the
> > > max values which is basically what my patch does.  There was some
> > > discussion about making determine_rate mandatory for muxes[1] and this
> > > patch should help with this in addition to making it easier to sync
> > > more video resolutions on the 8m Mini and Nano.
> >
> > Those patches have been queued by Stephen for 6.6 :)
> 
> One of the patches in the older series was reverted, but this was to
> address the patch that was reverted.

Was it? I haven't been cc'd and it doesn't seem to be in -next either?

Maxime

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