Re: [PATCH v1 5/5] mtd: nand: add support for the Sandisk SDTNQGAMA chip

[Miquel Raynal]

Hi Johan,

jbx6244@xxxxxxxxx wrote on Thu, 8 Jun 2023 18:31:04 +0200:

> Sandisk SDTNQGAMA is a 8GB size, 3.3V 8 bit chip with 16KB page size,
> 1KB write size and 40 bit ecc support
> 
> Signed-off-by: Paweł Jarosz <paweljarosz3691@xxxxxxxxx>

Pawel needs to be author of the patch or credited with a
co-developped-by+SoB otherwise. The current SoB lines are invalid.

> Signed-off-by: Johan Jonker <jbx6244@xxxxxxxxx>
> ---
>  drivers/mtd/nand/raw/nand_ids.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/mtd/nand/raw/nand_ids.c b/drivers/mtd/nand/raw/nand_ids.c
> index dacc5529b..53c4118de 100644
> --- a/drivers/mtd/nand/raw/nand_ids.c
> +++ b/drivers/mtd/nand/raw/nand_ids.c
> @@ -44,6 +44,9 @@ struct nand_flash_dev nand_flash_ids[] = {
>  	{"TC58NVG6D2 64G 3.3V 8-bit",
>  		{ .id = {0x98, 0xde, 0x94, 0x82, 0x76, 0x56, 0x04, 0x20} },
>  		  SZ_8K, SZ_8K, SZ_2M, 0, 8, 640, NAND_ECC_INFO(40, SZ_1K) },
> +	{"SDTNQGAMA 64G 3.3V 8-bit",
> +		{ .id = {0x45, 0xde, 0x94, 0x93, 0x76, 0x57} },
> +		  SZ_16K, SZ_8K, SZ_4M, 0, 6, 1280, NAND_ECC_INFO(40, SZ_1K) },

I guess you'll need a sandisk driver to reflect the missing timings?

>  	{"SDTNRGAMA 64G 3.3V 8-bit",
>  		{ .id = {0x45, 0xde, 0x94, 0x93, 0x76, 0x50} },
>  		  SZ_16K, SZ_8K, SZ_4M, 0, 6, 1280, NAND_ECC_INFO(40, SZ_1K) },
> --
> 2.30.2
> 


Thanks,
Miquèl