[PATCH v3 2/6] dt-bindings: clock: Add LPASS AUDIOCC and reset controller for SC8280XP

From: Srinivas Kandagatla
Date: Thu Jun 08 2023 - 08:53:45 EST


The LPASS (Low Power Audio Subsystem) Audio clock controller provides reset
support when it is under the control of Q6DSP.

Add support for those resets and adds IDs for clients to request the reset.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@xxxxxxxxxx>
Reviewed-by: Johan Hovold <johan+linaro@xxxxxxxxxx>
---
.../bindings/clock/qcom,sc8280xp-lpasscc.yaml | 10 ++++++++++
include/dt-bindings/clock/qcom,sc8280xp-lpasscc.h | 5 +++++
2 files changed, 15 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/qcom,sc8280xp-lpasscc.yaml b/Documentation/devicetree/bindings/clock/qcom,sc8280xp-lpasscc.yaml
index 047cae91f443..3326dcd6766c 100644
--- a/Documentation/devicetree/bindings/clock/qcom,sc8280xp-lpasscc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,sc8280xp-lpasscc.yaml
@@ -19,6 +19,7 @@ description: |
properties:
compatible:
enum:
+ - qcom,sc8280xp-lpassaudiocc
- qcom,sc8280xp-lpasscc

reg:
@@ -39,6 +40,15 @@ required:
additionalProperties: false

examples:
+ - |
+ #include <dt-bindings/clock/qcom,sc8280xp-lpasscc.h>
+ lpass_audiocc: clock-controller@32a9000 {
+ compatible = "qcom,sc8280xp-lpassaudiocc";
+ reg = <0x032a9000 0x1000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
- |
#include <dt-bindings/clock/qcom,sc8280xp-lpasscc.h>
lpasscc: clock-controller@33e0000 {
diff --git a/include/dt-bindings/clock/qcom,sc8280xp-lpasscc.h b/include/dt-bindings/clock/qcom,sc8280xp-lpasscc.h
index df800ea2741c..d190d57fc81a 100644
--- a/include/dt-bindings/clock/qcom,sc8280xp-lpasscc.h
+++ b/include/dt-bindings/clock/qcom,sc8280xp-lpasscc.h
@@ -6,6 +6,11 @@
#ifndef _DT_BINDINGS_CLK_QCOM_LPASSCC_SC8280XP_H
#define _DT_BINDINGS_CLK_QCOM_LPASSCC_SC8280XP_H

+/* LPASS AUDIO CC CSR */
+#define LPASS_AUDIO_SWR_RX_CGCR 0
+#define LPASS_AUDIO_SWR_WSA_CGCR 1
+#define LPASS_AUDIO_SWR_WSA2_CGCR 2
+
/* LPASS TCSR */
#define LPASS_AUDIO_SWR_TX_CGCR 0

--
2.25.1