Re: [PATCH V2 1/6] perf/x86/intel: Add Grand Ridge and Sierra Forest

[Liang, Kan]

Hi Peter,

On 2023-05-22 7:30 a.m., kan.liang@xxxxxxxxxxxxxxx wrote:
> From: Kan Liang <kan.liang@xxxxxxxxxxxxxxx>
> 
> The Grand Ridge and Sierra Forest are successors to Snow Ridge. They
> both have Crestmont core. From the core PMU's perspective, they are
> similar to the e-core of MTL. The only difference is the LBR event
> logging feature, which will be implemented in the following patches.
> 
> Create a non-hybrid PMU setup for Grand Ridge and Sierra Forest.
> 
> Reviewed-by: Andi Kleen <ak@xxxxxxxxxxxxxxx>
> Signed-off-by: Kan Liang <kan.liang@xxxxxxxxxxxxxxx>
> ---
> 


Gentle ping.

Do you have any comments for the patch set?

The patch set based on the perf/core branch which doesn't
include the latest fix, 90befef5a9e8 ("perf/x86: Fix missing sample size
update on AMD BRS").
https://lore.kernel.org/lkml/2f09023a-cccb-35df-da0a-d245ee5238be@xxxxxxxxxxxxxxx/

Should I rebase it on the perf/urgent and send the V3?


Thanks,
Kan


> No changes since V1.
> 
>  arch/x86/events/intel/core.c | 52 +++++++++++++++++++++++++++++++++++-
>  arch/x86/events/intel/ds.c   |  9 +++++--
>  arch/x86/events/perf_event.h |  2 ++
>  3 files changed, 60 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
> index a3fb996a86a1..ba2a971e6b8a 100644
> --- a/arch/x86/events/intel/core.c
> +++ b/arch/x86/events/intel/core.c
> @@ -2119,6 +2119,17 @@ static struct extra_reg intel_grt_extra_regs[] __read_mostly = {
>  	EVENT_EXTRA_END
>  };
>  
> +EVENT_ATTR_STR(topdown-retiring,       td_retiring_cmt,        "event=0x72,umask=0x0");
> +EVENT_ATTR_STR(topdown-bad-spec,       td_bad_spec_cmt,        "event=0x73,umask=0x0");
> +
> +static struct attribute *cmt_events_attrs[] = {
> +	EVENT_PTR(td_fe_bound_tnt),
> +	EVENT_PTR(td_retiring_cmt),
> +	EVENT_PTR(td_bad_spec_cmt),
> +	EVENT_PTR(td_be_bound_tnt),
> +	NULL
> +};
> +
>  static struct extra_reg intel_cmt_extra_regs[] __read_mostly = {
>  	/* must define OFFCORE_RSP_X first, see intel_fixup_er() */
>  	INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x800ff3ffffffffffull, RSP_0),
> @@ -4830,6 +4841,8 @@ PMU_FORMAT_ATTR(ldlat, "config1:0-15");
>  
>  PMU_FORMAT_ATTR(frontend, "config1:0-23");
>  
> +PMU_FORMAT_ATTR(snoop_rsp, "config1:0-63");
> +
>  static struct attribute *intel_arch3_formats_attr[] = {
>  	&format_attr_event.attr,
>  	&format_attr_umask.attr,
> @@ -4860,6 +4873,13 @@ static struct attribute *slm_format_attr[] = {
>  	NULL
>  };
>  
> +static struct attribute *cmt_format_attr[] = {
> +	&format_attr_offcore_rsp.attr,
> +	&format_attr_ldlat.attr,
> +	&format_attr_snoop_rsp.attr,
> +	NULL
> +};
> +
>  static struct attribute *skl_format_attr[] = {
>  	&format_attr_frontend.attr,
>  	NULL,
> @@ -5630,7 +5650,6 @@ static struct attribute *adl_hybrid_extra_attr[] = {
>  	NULL
>  };
>  
> -PMU_FORMAT_ATTR_SHOW(snoop_rsp, "config1:0-63");
>  FORMAT_ATTR_HYBRID(snoop_rsp,	hybrid_small);
>  
>  static struct attribute *mtl_hybrid_extra_attr_rtm[] = {
> @@ -6178,6 +6197,37 @@ __init int intel_pmu_init(void)
>  		name = "gracemont";
>  		break;
>  
> +	case INTEL_FAM6_GRANDRIDGE:
> +	case INTEL_FAM6_SIERRAFOREST_X:
> +		x86_pmu.mid_ack = true;
> +		memcpy(hw_cache_event_ids, glp_hw_cache_event_ids,
> +		       sizeof(hw_cache_event_ids));
> +		memcpy(hw_cache_extra_regs, tnt_hw_cache_extra_regs,
> +		       sizeof(hw_cache_extra_regs));
> +		hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1;
> +
> +		x86_pmu.event_constraints = intel_slm_event_constraints;
> +		x86_pmu.pebs_constraints = intel_grt_pebs_event_constraints;
> +		x86_pmu.extra_regs = intel_cmt_extra_regs;
> +
> +		x86_pmu.pebs_aliases = NULL;
> +		x86_pmu.pebs_prec_dist = true;
> +		x86_pmu.lbr_pt_coexist = true;
> +		x86_pmu.pebs_block = true;
> +		x86_pmu.flags |= PMU_FL_HAS_RSP_1;
> +		x86_pmu.flags |= PMU_FL_INSTR_LATENCY;
> +
> +		intel_pmu_pebs_data_source_cmt();
> +		x86_pmu.pebs_latency_data = mtl_latency_data_small;
> +		x86_pmu.get_event_constraints = cmt_get_event_constraints;
> +		x86_pmu.limit_period = spr_limit_period;
> +		td_attr = cmt_events_attrs;
> +		mem_attr = grt_mem_attrs;
> +		extra_attr = cmt_format_attr;
> +		pr_cont("Crestmont events, ");
> +		name = "crestmont";
> +		break;
> +
>  	case INTEL_FAM6_WESTMERE:
>  	case INTEL_FAM6_WESTMERE_EP:
>  	case INTEL_FAM6_WESTMERE_EX:
> diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c
> index a2e566e53076..608e220e46aa 100644
> --- a/arch/x86/events/intel/ds.c
> +++ b/arch/x86/events/intel/ds.c
> @@ -144,7 +144,7 @@ void __init intel_pmu_pebs_data_source_adl(void)
>  	__intel_pmu_pebs_data_source_grt(data_source);
>  }
>  
> -static void __init intel_pmu_pebs_data_source_cmt(u64 *data_source)
> +static void __init __intel_pmu_pebs_data_source_cmt(u64 *data_source)
>  {
>  	data_source[0x07] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOPX, FWD);
>  	data_source[0x08] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HITM);
> @@ -164,7 +164,12 @@ void __init intel_pmu_pebs_data_source_mtl(void)
>  
>  	data_source = x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX].pebs_data_source;
>  	memcpy(data_source, pebs_data_source, sizeof(pebs_data_source));
> -	intel_pmu_pebs_data_source_cmt(data_source);
> +	__intel_pmu_pebs_data_source_cmt(data_source);
> +}
> +
> +void __init intel_pmu_pebs_data_source_cmt(void)
> +{
> +	__intel_pmu_pebs_data_source_cmt(pebs_data_source);
>  }
>  
>  static u64 precise_store_data(u64 status)
> diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h
> index d6de4487348c..c8ba2be7585d 100644
> --- a/arch/x86/events/perf_event.h
> +++ b/arch/x86/events/perf_event.h
> @@ -1606,6 +1606,8 @@ void intel_pmu_pebs_data_source_grt(void);
>  
>  void intel_pmu_pebs_data_source_mtl(void);
>  
> +void intel_pmu_pebs_data_source_cmt(void);
> +
>  int intel_pmu_setup_lbr_filter(struct perf_event *event);
>  
>  void intel_pt_interrupt(void);