Re: [PATCH v12 12/31] LoongArch: KVM: Implement vcpu interrupt operations

[Tianrui Zhao]

在 2023年06月06日 14:49, Youling Tang 写道:
> On 05/30/2023 09:52 AM, Tianrui Zhao wrote:
> > Implement vcpu interrupt operations such as vcpu set irq and
> > vcpu clear irq, using set_gcsr_estat to set irq which is
> > parsed by the irq bitmap.
> >
> > Signed-off-by: Tianrui Zhao <zhaotianrui@xxxxxxxxxxx>
> > ---
> >  arch/loongarch/kvm/interrupt.c | 127 +++++++++++++++++++++++++++++++++
> >  arch/loongarch/kvm/vcpu.c      |  45 ++++++++++++
> >  2 files changed, 172 insertions(+)
> >  create mode 100644 arch/loongarch/kvm/interrupt.c
> >
> > diff --git a/arch/loongarch/kvm/interrupt.c 
> > b/arch/loongarch/kvm/interrupt.c
> > new file mode 100644
> > index 000000000000..243bb19b387e
> > --- /dev/null
> > +++ b/arch/loongarch/kvm/interrupt.c
> > @@ -0,0 +1,127 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Copyright (C) 2020-2023 Loongson Technology Corporation Limited
> > + */
> > +
> > +#include <linux/errno.h>
> > +#include <linux/err.h>
> > +#include <asm/kvm_vcpu.h>
> > +#include <asm/kvm_csr.h>
> > +
> > +static unsigned int int_to_coreint[EXCCODE_INT_NUM] = {
> > +    [INT_TI]    = CPU_TIMER,
> > +    [INT_IPI]    = CPU_IPI,
> > +    [INT_SWI0]    = CPU_SIP0,
> > +    [INT_SWI1]    = CPU_SIP1,
> > +    [INT_HWI0]    = CPU_IP0,
> > +    [INT_HWI1]    = CPU_IP1,
> > +    [INT_HWI2]    = CPU_IP2,
> > +    [INT_HWI3]    = CPU_IP3,
> > +    [INT_HWI4]    = CPU_IP4,
> > +    [INT_HWI5]    = CPU_IP5,
> > +    [INT_HWI6]    = CPU_IP6,
> > +    [INT_HWI7]    = CPU_IP7,
> > +};
> > +
> > +static int _kvm_irq_deliver(struct kvm_vcpu *vcpu, unsigned int 
> > priority)
> > +{
> > +    unsigned int irq = 0;
> > +
> > +    clear_bit(priority, &vcpu->arch.irq_pending);
> > +    if (priority < EXCCODE_INT_NUM)
> > +        irq = int_to_coreint[priority];
> > +
> > +    switch (priority) {
> > +    case INT_TI:
> > +    case INT_IPI:
> > +    case INT_SWI0:
> > +    case INT_SWI1:
> > +        set_gcsr_estat(irq);
> > +        break;
> > +
> > +    case INT_HWI0:
> > +    case INT_HWI1:
> > +    case INT_HWI2:
> > +    case INT_HWI3:
> > +    case INT_HWI4:
> > +    case INT_HWI5:
> > +    case INT_HWI6:
> > +    case INT_HWI7:
> It can be simplified to,
> case INT_HWI0 ... INT_HWI7:
Thanks, I will simplify those case statement.

Thanks
Tianrui Zhao
> > +        set_csr_gintc(irq);
> > +        break;
> > +
> > +    default:
> > +        break;
> > +    }
> > +
> > +    return 1;
> > +}
> > +
> > +static int _kvm_irq_clear(struct kvm_vcpu *vcpu, unsigned int priority)
> > +{
> > +    unsigned int irq = 0;
> > +
> > +    clear_bit(priority, &vcpu->arch.irq_clear);
> > +    if (priority < EXCCODE_INT_NUM)
> > +        irq = int_to_coreint[priority];
> > +
> > +    switch (priority) {
> > +    case INT_TI:
> > +    case INT_IPI:
> > +    case INT_SWI0:
> > +    case INT_SWI1:
> > +        clear_gcsr_estat(irq);
> > +        break;
> > +
> > +    case INT_HWI0:
> > +    case INT_HWI1:
> > +    case INT_HWI2:
> > +    case INT_HWI3:
> > +    case INT_HWI4:
> > +    case INT_HWI5:
> > +    case INT_HWI6:
> > +    case INT_HWI7:
> ditto.
>
> Thanks,
> Youling
> > +        clear_csr_gintc(irq);
> > +        break;
> > +
> > +    default:
> > +        break;
> > +    }
> > +
> > +    return 1;
> > +}