[PATCH 0/2] clk: sunxi-ng: Consider alternative parent rates when determining NKM clock rate

From: Frank Oltmanns
Date: Mon Jun 05 2023 - 15:08:43 EST


I would like to share a patchset that enables the NKM clock in pll-video0 to
consider alternative parent rates. I have found this feature particularly useful
to adjust the pll-video0's clock on Allwinner A64, as it allows me to achieve an
optimal rate for driving the board's panel (in my case, the Pinephone).

To provide some context, the clock structure involved in this process is as follows:
clock clock type
--------------------------------------
pll-video0 ccu_nm
pll-mipi ccu_nkm
tcon0 ccu_mux
tcon-data-clock sun4i_dclk

The divider between tcon0 and tcon-data-clock is fixed at 4. Therefore, in order
to achieve a rate that closely matches the desired rate of the panel, I need
pll-mipi to operate at a specific rate.

However, I must emphasize that setting the parent's rate for NKM clocks results
in a significant increase in the time required to find the optimal rate. For
instance, setting DCLK on the pinephone has seen a 60-fold increase in the time
taken, from approximately 0.5 ms to around 30 ms. These figures were obtained
through informal measurements on my pinephone, involving kernel logging and a
few reboots. The worst-case scenario observed was approximately 37 ms, while the
majority of cases were just under 30 ms.

The reason for this considerable increase in time is that the code now iterates
over all combinations of NKM for pll-mipi. For each combination, it subsequently
iterates over all combinations of NM for pll-video0.

I greatly appreciate your feedback and suggestions for further improving this
patchset.

Thanks,
Frank

Frank Oltmanns (2):
clk: sunxi-ng: nkm: consider alternative parent rates when finding
rate
clk: sunxi-ng: a64: allow pll-mipi to set parent's rate

drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 3 +-
drivers/clk/sunxi-ng/ccu_nkm.c | 40 +++++++++++++++++++++------
2 files changed, 33 insertions(+), 10 deletions(-)

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2.40.1