Re: [PATCH] drm/amdgpu: fix xclk freq on CHIP_STONEY

From: Alex Deucher
Date: Fri Jun 02 2023 - 14:20:42 EST


Applied. Thanks!

Alex

On Thu, Jun 1, 2023 at 5:48 PM Chia-I Wu <olvaffe@xxxxxxxxx> wrote:
>
> According to Alex, most APUs from that time seem to have the same issue
> (vbios says 48Mhz, actual is 100Mhz). I only have a CHIP_STONEY so I
> limit the fixup to CHIP_STONEY
> ---
> drivers/gpu/drm/amd/amdgpu/vi.c | 11 +++++++++--
> 1 file changed, 9 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
> index 770f2d7a371fc..6a8494f98d3ef 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vi.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vi.c
> @@ -542,8 +542,15 @@ static u32 vi_get_xclk(struct amdgpu_device *adev)
> u32 reference_clock = adev->clock.spll.reference_freq;
> u32 tmp;
>
> - if (adev->flags & AMD_IS_APU)
> - return reference_clock;
> + if (adev->flags & AMD_IS_APU) {
> + switch (adev->asic_type) {
> + case CHIP_STONEY:
> + /* vbios says 48Mhz, but the actual freq is 100Mhz */
> + return 10000;
> + default:
> + return reference_clock;
> + }
> + }
>
> tmp = RREG32_SMC(ixCG_CLKPIN_CNTL_2);
> if (REG_GET_FIELD(tmp, CG_CLKPIN_CNTL_2, MUX_TCLK_TO_XCLK))
> --
> 2.41.0.rc0.172.g3f132b7071-goog
>