Re: [PATCH v2 1/2] spi: spi-cadence: Interleave write of TX and read of RX FIFO

[Mark Brown]

On Thu, 18 May 2023 10:39:26 +0100, Charles Keepax wrote:
> When working in slave mode it seems the timing is exceedingly tight.
> The TX FIFO can never empty, because the master is driving the clock so
> zeros would be sent for those bytes where the FIFO is empty.
> 
> Return to interleaving the writing of the TX FIFO and the reading
> of the RX FIFO to try to ensure the data is available when required.
> 
> [...]

Applied to

   https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-next

Thanks!

[1/2] spi: spi-cadence: Interleave write of TX and read of RX FIFO
      commit: 6afe2ae8dc48e643cb9f52e86494b96942440bc6

All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.

You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying
to this mail.

Thanks,
Mark