Re: [PATCH V6 5/6] drm: bridge: samsung-dsim: Dynamically configure DPHY timing

[Jagan Teki]

On Tue, May 16, 2023 at 5:27 AM Adam Ford <aford173@xxxxxxxxx> wrote:
>
> The DPHY timings are currently hard coded. Since the input
> clock can be variable, the phy timings need to be variable
> too.  To facilitate this, we need to cache the hs_clock
> based on what is generated from the PLL.
>
> The phy_mipi_dphy_get_default_config_for_hsclk function
> configures the DPHY timings in pico-seconds, and a small macro
> converts those timings into clock cycles based on the hs_clk.
>
> Signed-off-by: Adam Ford <aford173@xxxxxxxxx>
> Signed-off-by: Lucas Stach <l.stach@xxxxxxxxxxxxxx>
> Tested-by: Chen-Yu Tsai <wenst@xxxxxxxxxxxx>
> Tested-by: Frieder Schrempf <frieder.schrempf@xxxxxxxxxx>
> Reviewed-by: Frieder Schrempf <frieder.schrempf@xxxxxxxxxx>
> Tested-by: Michael Walle <michael@xxxxxxxx>
> ---

Tested-by: Jagan Teki <jagan@xxxxxxxxxxxxxxxxxxxx> # imx8mm-icore