Re: [PATCH 1/2] arm64: dts: qcom: sm8550-qrd: add PCIe0

[Dmitry Baryshkov]

On Tue, 16 May 2023 at 16:30, Krzysztof Kozlowski
<krzysztof.kozlowski@xxxxxxxxxx> wrote:
>
> Add PCIe0 nodes used with WCN7851 device.  The PCIe1 is not connected,
> thus skip pcie_1_phy_aux_clk input clock to GCC.
>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx>
> ---
>  arch/arm64/boot/dts/qcom/sm8550-qrd.dts | 32 +++++++++++++++++++++++++
>  1 file changed, 32 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts
> index ccc58e6b45bd..e7a2bc5d788b 100644
> --- a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts
> +++ b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts
> @@ -385,6 +385,38 @@ vreg_l3g_1p2: ldo3 {
>         };
>  };
>
> +&gcc {
> +       clocks = <&bi_tcxo_div2>, <&sleep_clk>,
> +                <&pcie0_phy>,
> +                <&pcie1_phy>,
> +                <0>,
> +                <&ufs_mem_phy 0>,
> +                <&ufs_mem_phy 1>,
> +                <&ufs_mem_phy 2>,
> +                <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>;
> +};

Is there any reason to disable the PCIe1 PHY AUX clock here? I mean,
the PCIe1 is still enabled in the hardware.

> +
> +&pcie_1_phy_aux_clk {
> +       status = "disabled";
> +};
> +
> +&pcie0 {
> +       wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
> +       perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
> +
> +       pinctrl-0 = <&pcie0_default_state>;
> +       pinctrl-names = "default";
> +
> +       status = "okay";
> +};
> +
> +&pcie0_phy {
> +       vdda-phy-supply = <&vreg_l1e_0p88>;
> +       vdda-pll-supply = <&vreg_l3e_1p2>;
> +
> +       status = "okay";
> +};
> +
>  &qupv3_id_0 {
>         status = "okay";
>  };
> --
> 2.34.1
>


-- 
With best wishes
Dmitry