Re: [PATCH 1/2] PCI: pciehp: Add support for OS-First Hotplug and AER/DPC

[Smita Koralahalli]

On 5/15/2023 12:38 PM, Lukas Wunner wrote:
> On Mon, May 15, 2023 at 12:20:42PM -0700, Smita Koralahalli wrote:
> > On 5/11/2023 8:23 AM, Lukas Wunner wrote:
> > > Subject: [PATCH] PCI: pciehp: Disable Surprise Down Error reporting
[...]
> > I have logged in the status registers after the device is removed in
> > pciehp_handle_presence_or_link_change().
> [...]
> > Section 6.2.3.2.2 in PCIe Spec v6.0 has also mentioned that:
> > "If an individual error is masked when it is detected, its error status bit
> > is still affected, but no error reporting Message is sent to the Root
> > Complex, and the error is not recorded in the Header Log, TLP Prefix Log, or
> > First Error Pointer"..
>
> Thanks for the thorough testing.  So the error is logged and next time
> a reporting message for a different error is sent to the Root Complex,
> that earlier Surprise Down Error will be seen and you'd get belated
> log messages for it, is that what you're saying?

Yes, thereby confusing user on a false error.
> I guess I could amend the patch to let pciehp unconditionally clear
> the Surprise Down Error Status bit upon a DLLSC event.

OK. First, mask the uncorrected AER status register for surprise down 
during initialization and then clear all status registers 
unconditionally including DPC_RP_PIO and others inside 
pciehp_handle_presence_or_link_change()..?

Could I please know, why do you think masking surprise down during 
initialization would be a better approach than reading surprise down 
error status on a DPC event? Because in both approaches we should be 
however clearing status registers right?

> Does the patch otherwise do what you want, i.e. no irritating messages
> and no extra delay incurred by AER/DPC handling?

no irritating messages and no delay as there is no DPC error logged now.

Thanks,
Smita
> Thanks!
>
> Lukas