Re: [PATCH 1/2] spi: spi-cadence: Avoid read of RX FIFO before its ready

[Charles Keepax]

On Mon, May 15, 2023 at 12:04:38PM +0000, Goud, Srinivas wrote:
> >-----Original Message-----
> >From: Charles Keepax <ckeepax@xxxxxxxxxxxxxxxxxxxxx>
> >Sent: Tuesday, May 9, 2023 10:12 PM
> >To: broonie@xxxxxxxxxx
> >Cc: Goud, Srinivas <srinivas.goud@xxxxxxx>; linux-spi@xxxxxxxxxxxxxxx;
> >linux-kernel@xxxxxxxxxxxxxxx; patches@xxxxxxxxxxxxxxxxxxxxx
> >Subject: [PATCH 1/2] spi: spi-cadence: Avoid read of RX FIFO before its ready
> >-		while (trans_cnt) {
> >-			cdns_spi_read_rx_fifo(xspi, 1);
> >-
> >-			if (xspi->tx_bytes) {
> >-				if (xspi->txbuf)
> >-					cdns_spi_write(xspi, CDNS_SPI_TXD,
> >-						       *xspi->txbuf++);
> >-				else
> >-					cdns_spi_write(xspi, CDNS_SPI_TXD,
> >0);
> >-				xspi->tx_bytes--;
> >-			}
> >-			trans_cnt--;
> >-		}
> >-		if (!xspi->tx_bytes) {
> >-			/* Fixed delay due to controller limitation with
> >-			 * RX_NEMPTY incorrect status
> >-			 * Xilinx AR:65885 contains more details
> >-			 */
> >-			udelay(10);
> >-			cdns_spi_read_rx_fifo(xspi, xspi->rx_bytes);
> >+		cdns_spi_read_rx_fifo(xspi, trans_cnt);
> Cadence SPI configured in Slave mode,  when threshold is half of FIFO depth cdns_spi_read_rx_fifo() function continuously in read mode, 
> due to this we see incorrect data received on the Master side as Slave is failed to update the TX FIFO on time.

Apologies I am having a little trouble following this are you
saying this part of the patch cases issues for you running in
slave mode?

Thanks,
Charles