[PATCH v4 0/6] firmware: tegra: Add MRQ support for Tegra264.
From: Peter De Schrijver
Date: Thu May 11 2023 - 09:23:34 EST
In Tegra264 the carveouts (GSCs) used to communicate between BPMP and
CPU-NS may reside in DRAM. The location will be signalled using reserved
memory node in DT. Additionally some minor updates to the HSP driver are
done to support the new chip.
Peter De Schrijver (4):
dt-bindings: mailbox: tegra: Document Tegra264 HSP
dt-bindings: Add support for DRAM MRQ GSCs
dt-bindings: Add support for tegra186-bpmp DRAM MRQ GSCs
firmware: tegra: bpmp: Add support for DRAM MRQ GSCs
Stefan Kristiansson (2):
mailbox: tegra: add support for Tegra264
soc/tegra: fuse: Add support for Tegra264
Changes in v2:
- Added signoff messages
- Updated bindings to support DRAM MRQ GSCs
- Split out memory-region property for tegra186-bpmp into its own patch
- Addressed sparse errors in bpmp-tegra186.c
Changes in v3:
- Added #address-cells = <2> and #size-cells = <2> to
nvidia,tegra264-bpmp-shmem binding example.
Changes in v4:
- Added lost Acked-by tags to patch 1 and 2.
- Updated topic for patch 3 to 'soc/tegra: fuse:'.
- Updated topic for patch 4 to 'dt-bindings: Add support for DRAM MRQ GSCs'.
- Updated topic for patch 5 to 'dt-bindings: Add support for tegra186-bpmp DRAM MRQ GSCs'.
- Removed unneeded include statements in patch 6.
- Renamed some functions in patch 6 for more consistent naming.
- Improved handling of void * vs void __iomem * in patch6 .
.../firmware/nvidia,tegra186-bpmp.yaml | 37 ++-
.../bindings/mailbox/nvidia,tegra186-hsp.yaml | 1 +
.../nvidia,tegra264-bpmp-shmem.yaml | 47 ++++
drivers/firmware/tegra/bpmp-tegra186.c | 232 +++++++++++++-----
drivers/firmware/tegra/bpmp.c | 4 +-
drivers/mailbox/tegra-hsp.c | 16 +-
drivers/soc/tegra/fuse/tegra-apbmisc.c | 3 +-
include/soc/tegra/fuse.h | 3 +-
8 files changed, 268 insertions(+), 75 deletions(-)
create mode 100644 Documentation/devicetree/bindings/reserved-memory/nvidia,tegra264-bpmp-shmem.yaml
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2.34.1