[PATCH] mips: dts: ralink: Clarify usage of MT7621 ethernet phy arguments

[Liviu Dudau]

The device tree uses numbers as arguments to the phys property that are
confusing for newcomers. Define names for the values and use them in the
device tree.

Signed-off-by: Liviu Dudau <liviu@xxxxxxxxxxx>
---
 arch/mips/boot/dts/ralink/mt7621.dtsi | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/arch/mips/boot/dts/ralink/mt7621.dtsi b/arch/mips/boot/dts/ralink/mt7621.dtsi
index 7caed0d14f11a..1c584b6d0e1fa 100644
--- a/arch/mips/boot/dts/ralink/mt7621.dtsi
+++ b/arch/mips/boot/dts/ralink/mt7621.dtsi
@@ -4,6 +4,9 @@
 #include <dt-bindings/clock/mt7621-clk.h>
 #include <dt-bindings/reset/mt7621-reset.h>
 
+#define DUAL_PORT   1
+#define SINGLE_PORT 0
+
 / {
 	#address-cells = <1>;
 	#size-cells = <1>;
@@ -455,7 +458,7 @@ pcie@0,0 {
 			interrupt-map = <0 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>;
 			resets = <&sysc MT7621_RST_PCIE0>;
 			clocks = <&sysc MT7621_CLK_PCIE0>;
-			phys = <&pcie0_phy 1>;
+			phys = <&pcie0_phy DUAL_PORT>;
 			phy-names = "pcie-phy0";
 			ranges;
 		};
@@ -470,7 +473,7 @@ pcie@1,0 {
 			interrupt-map = <0 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>;
 			resets = <&sysc MT7621_RST_PCIE1>;
 			clocks = <&sysc MT7621_CLK_PCIE1>;
-			phys = <&pcie0_phy 1>;
+			phys = <&pcie0_phy DUAL_PORT>;
 			phy-names = "pcie-phy1";
 			ranges;
 		};
@@ -485,7 +488,7 @@ pcie@2,0 {
 			interrupt-map = <0 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
 			resets = <&sysc MT7621_RST_PCIE2>;
 			clocks = <&sysc MT7621_CLK_PCIE2>;
-			phys = <&pcie2_phy 0>;
+			phys = <&pcie2_phy SINGLE_PORT>;
 			phy-names = "pcie-phy2";
 			ranges;
 		};
-- 
2.40.0