Re: [PATCH v5 0/5] PCI: brcmstb: Configure appropriate HW CLKREQ# mode

[Jim Quinlan]

On Tue, May 9, 2023 at 3:47 AM Cyril Brulebois <kibi@xxxxxxxxxx> wrote:
>
> Hi Jim,
>
> Jim Quinlan <jim2101024@xxxxxxxxx> (2023-05-08):
> > v5 -- Remove DT property "brcm,completion-timeout-us" from
> >       "DT bindings" commit.  Although this error may be reported
> >       as a completion timeout, its cause was traced to an
> >       internal bus timeout which may occur even when there is
> >       no PCIe access being processed.  We set a timeout of four
> >       seconds only if we are operating in "L1SS CLKREQ#" mode.
> >    -- Correct CEM 2.0 reference provided by HW engineer,
> >       s/3.2.5.2.5/3.2.5.2.2/ (Bjorn)
> >    -- Add newline to dev_info() string (Stefan)
> >    -- Change variable rval to unsigned (Stefan)
> >    -- s/implementaion/implementation/ (Bjorn)
> >    -- s/superpowersave/powersupersave/ (Bjorn)
> >    -- Slightly modify message on "PERST#" commit.
> >    -- Rebase to torvalds master
>
> Same results as with v4: looks good to me!
>
> Using an official CM4 IO Board, I've successfully tested the same 9
> setups as before, combining each:
>  - CM4 Lite Rev 1.0
>  - CM4 8/32 Rev 1.0
>  - CM4 4/32 Rev 1.1
>
> with each off-the-shelf PCIe/USB adapter at my disposal:
>  - SupaHub PCE6U1C-R02, VER 006
>  - SupaHub PCE6U1C-R02, VER 006S
>  - Waveshare based on VIA VL805/806
>
> Each system boots successfully, exposes the Kingston memory stick
> plugged onto the PCIe/USB adapter, and happily reads data from it.
>
> Note: I only tested each CM4 with the upgraded EEPROM (2023-01-11),
> and without tweaking the DTB (i.e. without adding brcm,enable-l1ss).
>
>
> Tested-By: Cyril Brulebois <cyril@xxxxxxxxxxx>

Thanks a lot for doing this Cyril!
>
>
> Cheers,
> --
> Cyril Brulebois (kibi@xxxxxxxxxx)            <https://debamax.com/>
> D-I release manager -- Release team member -- Freelance Consultant

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