[RFC PATCH v2] arm64: dts: ti: k3-j721s2: Add reserved status in msmc node.

[Udit Kumar]

TI K3 SOCs have msmc sram, part of it can be configured as L3 cache
depending upon system firmware configuration file.

This could be possible to have no L3 cache or variable size of
L3 cache.
In either case top of 64KB of SRAM has to be reserved for system
firmware called tifs.

https://software-dl.ti.com/tisci/esd/latest/2_tisci_msgs/general/core.html?highlight=msmc
Section: TISCI_MSG_QUERY_MSMC.

But u-boot as part of fix up is deleting sysfw and l3cache node
before passing DT to OS
https://github.com/u-boot/u-boot/blob/master/arch/arm/mach-k3/common.c#L412

But keeping tifs subnode as is, tifs subnode memory region is also not
accessible to OS.

In my view we can handle in two ways
1) delete tifs node as well
In this case, only accessible sram will be visible to OS
https://lore.kernel.org/all/20230420081128.3617214-1-u-kumar1@xxxxxx/

2) make these nodes (tifs, atf and l3cache) as reserved,
so that OS has complete view of memory.

This is patch for option 2 to mark atf, l3-cache and tifs as
reserved. and let u-boot to set correct size for these nodes
as part of runtime fixup.

Nishanth suggested to discuss in k.org group
https://lore.kernel.org/all/20230502230022.5pjywy6h7oqrkmwh@elusive/

So sending this patch for suggestion for selection right option.
Also other options are welcome.


Signed-off-by: Udit Kumar <u-kumar1@xxxxxx>
---
Changes since v1:
https://lore.kernel.org/all/20230503144706.1265672-1-u-kumar1@xxxxxx/
- remove cover letter for 1 patch

 arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
index 2dd7865f7654..791993060f44 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
@@ -14,14 +14,17 @@ msmc_ram: sram@70000000 {
 		ranges = <0x0 0x0 0x70000000 0x400000>;
 
 		atf-sram@0 {
+			status = "reserved";
 			reg = <0x0 0x20000>;
 		};
 
 		tifs-sram@1f0000 {
+			status = "reserved";
 			reg = <0x1f0000 0x10000>;
 		};
 
 		l3cache-sram@200000 {
+			status = "reserved";
 			reg = <0x200000 0x200000>;
 		};
 	};
-- 
2.34.1