Re: [PATCH v2 3/5] ACPI/PCI: Add AER bits #defines for PCIe to PCI/PCI-X Bridge

[Bjorn Helgaas]

On Tue, Apr 18, 2023 at 10:38:58AM +0800, LeoLiuoc wrote:
> 在 2023/4/13 0:10, Bjorn Helgaas 写道:
> > On Wed, Apr 12, 2023 at 05:49:55PM +0800, LeoLiuoc wrote:

> > > >     ...
> > > >     #define PCI_ERR_ROOT_ERR_SRC    0x34    /* Error Source Identification */
> > > >     #define PCI_ERR_UNCOR_MASK2     0x30    /* PCIe to PCI/PCI-X bridge */
> > > >     #define PCI_ERR_UNCOR_SEVER2    0x34    /* PCIe to PCI/PCI-X bridge */
> > > >     #define PCI_ERR_CAP2            0x38    /* PCIe to PCI/PCI-X bridge */
> > > 
> > > I don't seem to understand what you mean. PCI_ERR_UNCOR_MASK2,
> > > PCI_ERR_UNCOR_SEVER2, and PCI_ERR_CAP2 represent the control and handling of
> > > individual errors that occur on traditional PCI or PCI-x secondary bus
> > > interfaces, these registers are valid only for Bridge. Although
> > > PCI_ERR_ROOT_ERR_SRC and PCI_ERR_UNCOR_SEVER2 have the same value, they
> > > represent register definitions for different device types.
> > 
> > Right.  I just don't want the blank line in the middle because it
> > might be mistaken for items in a different capability.  All the other
> > AER capability registers are defined together in a block, with no
> > blank lines in the middle, so I think these new ones should be part of
> > that block.
> 
> Ok，I see your point. Do you think this line of comment is still necessary?
> /* PCIe advanced error reporting extended capabilities for PCIe to PCI/PCI-X
> Bridge */

I suggested a trailing comment ("PCIe to PCI/PCI-X bridge").  If we
use that, I don't think the other is necessary.

Bjorn