Re: arch/mips/include/asm/timex.h:75:10: error: instruction requires a CPU feature not currently enabled

[Jiaxun Yang]

> 2023年4月24日 21:01，Nathan Chancellor <nathan@xxxxxxxxxx> 写道：
> 
> On Thu, Apr 20, 2023 at 12:41:50AM +0100, Jiaxun Yang wrote:
>> 
>> 
>>> 2023年4月20日 00:18，Nathan Chancellor <nathan@xxxxxxxxxx> 写道：
>>> 
>>> + Jiaxun, who has been looking into MIPS + LLVM issues recently and has
>>> been a big help :)
>> 
>> I think this patch[1] may fix the problem.
> 
> I have the following patch stack:
> 
> $ git log --oneline origin/master^..
> c6cd9f17692e MIPS: Replace assembly isa level directives with macros
> 60508ba7d92f MIPS: Limit MIPS_MT_SMP support by ISA reversion
> c9e250105de4 MIPS: Fallback CPU -march CFLAG to ISA level if unsupported
> 49c0420e59bb MIPS: Remove cc-option checks for -march=octeon
> b7ea7e959023 MIPS: Detect toolchain support of o32 ABI with 64 bit CPU
> 51f2d93245ba MIPS: Detect toolchain support of workarounds in Kconfig
> 7382a07eb105 MIPS: Add toolchain feature dependency for microMIPS smartMIPS
> de0621fbedd3 MIPS: Move various toolchain ASE check to Kconfig
> 3b85b9b39960 Add linux-next specific files for 20230424
> 
> but with the robot's configuration, I still see that error. I notice
> that the 'if (sel == 0)' branch of ___read_32bit_c0_register() has no
> '.set push' directive, could that matter here?

Sorry I was identifying the wrong problem.

The real problem is LLVM IAS (or the whole LLVM stack)’s microMIPS is broken,
It unable to handle “mfc0” and many other instructions.

Perhaps we should come up a method to block this config to happen.

Thanks
Jiaxun

> 
> Cheers,
> Nathan