Re: [PATCH v2] PCI: cadence: Fix Gen2 Link Retraining process

[Lorenzo Pieralisi]

On Wed, 15 Mar 2023 12:38:00 +0530, Siddharth Vadapalli wrote:
> The Link Retraining process is initiated to account for the Gen2 defect in
> the Cadence PCIe controller in J721E SoC. The errata corresponding to this
> is i2085, documented at:
> https://www.ti.com/lit/er/sprz455c/sprz455c.pdf
> 
> The existing workaround implemented for the errata waits for the Data Link
> initialization to complete and assumes that the link retraining process
> at the Physical Layer has completed. However, it is possible that the
> Physical Layer training might be ongoing as indicated by the
> PCI_EXP_LNKSTA_LT bit in the PCI_EXP_LNKSTA register.
> 
> [...]

Applied to controller/cadence, thanks!

[1/1] PCI: cadence: Fix Gen2 Link Retraining process
      https://git.kernel.org/pci/pci/c/eac223e85208

Thanks,
Lorenzo