Re: [PATCH] perf/x86/intel/uncore: add events for Intel SPR IMC PMU

[Liang, Kan]

On 2023-04-19 5:42 p.m., Stephane Eranian wrote:
> Add missing clockticks and cas_count_* events for Intel SapphireRapids IMC
> PMU. These events are useful to measure memory bandwidth.
> 
> Signed-off-by: Stephane Eranian <eranian@xxxxxxxxxx>

Reviewed-by: Kan Liang <kan.liang@xxxxxxxxxxxxxxx>

Thanks,
Kan

> ---
>  arch/x86/events/intel/uncore_snbep.c | 12 ++++++++++++
>  1 file changed, 12 insertions(+)
> 
> diff --git a/arch/x86/events/intel/uncore_snbep.c b/arch/x86/events/intel/uncore_snbep.c
> index 7d1199554fe3..fa9b209a11fa 100644
> --- a/arch/x86/events/intel/uncore_snbep.c
> +++ b/arch/x86/events/intel/uncore_snbep.c
> @@ -6068,6 +6068,17 @@ static struct intel_uncore_ops spr_uncore_mmio_ops = {
>  	.read_counter		= uncore_mmio_read_counter,
>  };
>  
> +static struct uncore_event_desc spr_uncore_imc_events[] = {
> +	INTEL_UNCORE_EVENT_DESC(clockticks,      "event=0x01,umask=0x00"),
> +	INTEL_UNCORE_EVENT_DESC(cas_count_read,  "event=0x05,umask=0xcf"),
> +	INTEL_UNCORE_EVENT_DESC(cas_count_read.scale, "6.103515625e-5"),
> +	INTEL_UNCORE_EVENT_DESC(cas_count_read.unit, "MiB"),
> +	INTEL_UNCORE_EVENT_DESC(cas_count_write, "event=0x05,umask=0xf0"),
> +	INTEL_UNCORE_EVENT_DESC(cas_count_write.scale, "6.103515625e-5"),
> +	INTEL_UNCORE_EVENT_DESC(cas_count_write.unit, "MiB"),
> +	{ /* end: all zeroes */ },
> +};
> +
>  static struct intel_uncore_type spr_uncore_imc = {
>  	SPR_UNCORE_COMMON_FORMAT(),
>  	.name			= "imc",
> @@ -6075,6 +6086,7 @@ static struct intel_uncore_type spr_uncore_imc = {
>  	.fixed_ctr		= SNR_IMC_MMIO_PMON_FIXED_CTR,
>  	.fixed_ctl		= SNR_IMC_MMIO_PMON_FIXED_CTL,
>  	.ops			= &spr_uncore_mmio_ops,
> +	.event_descs		= spr_uncore_imc_events,
>  };
>  
>  static void spr_uncore_pci_enable_event(struct intel_uncore_box *box,