Re: [PATCH v5 2/2] spi: dw: Add dma controller capability checks

[Serge Semin]

On Tue, Apr 11, 2023 at 03:18:34PM +0300, Andy Shevchenko wrote:
> On Thu, Mar 30, 2023 at 06:34:50AM +0000, Joy Chakraborty wrote:
> > Check capabilities of DMA controller during init to make sure it is
> > capable of handling MEM2DEV for tx channel, DEV2MEM for rx channel
> > and store addr_width capabilities to check per transfer to make sure the
> > bits/word requirement can be met for that transfer.
> 
> ...
> 
> > +static enum dma_slave_buswidth dw_spi_dma_convert_width(u8 n_bytes);
> 
> Can we avoid forward declarations please?
> 
> ...
> 
> > +	if (!(tx.directions & BIT(DMA_MEM_TO_DEV) &&
> > +	      rx.directions & BIT(DMA_DEV_TO_MEM)))
> > +		return -ENXIO;
> 

> What about simplex transfers where we only care about sending or receiving data
> and using dummy data for the other channel? Doesn't this make a regression for
> that types of transfers? (Or, if we don't support such, this should be explained
> in the commit message at least.)

I don't think the code above is that much relevant for the half-duplex
transfers. The DW APB SSI-DMA driver requires both Tx and Rx channels
being specified thus supporting the Full-duplex transfers at least in
case of the TxRx and Rx-only SPI-transfers (the later case relies on
having the dummy buffers supplied by the SPI-core). Thus the channels
must support the corresponding DMA-directions.

Indeed the Tx-only DMA-based SPI-transfers implementation in the
driver implies not using the Rx DMA-channel, but even in that case the
Rx-channel still needs to be specified otherwise the DW APB SSI-DMA
setup methods will halt with error returned. So unless there are cases
with dummy Rx DMA-channels (which I very much doubt there is) I don't
see the suggested update causing a regression. Am I missing something?

> 
> ...
> 
> > +	/*
> > +	 * Assuming both channels belong to the same DMA controller hence the
> > +	 * address width capabilities most likely would be the same.
> > +	 */
> > +	dws->dma_addr_widths = tx.dst_addr_widths & rx.src_addr_widths;
> 

> I don't think so this is correct.
> 
> Theoretically it's possible to have simplex transfers on which the one of
> the channel is simply ignored / not used. See above.

Please see my explanation above. To cut it short even in case of the
half-duplex SPI-xfers both channels need to be specified with the
respective capabilities. It's implied by the DW APB SSI-DMA setup
methods design (see dw_spi_dma_init_mfld() and
dw_spi_dma_init_generic()).

So until the DW APB SSI-DMA driver is re-developed to supporting true
Tx-only and Rx-only transfers with no requirement one of the channels
being specified I don't see any problem with the code above. Do you
still think otherwise?

-Serge(y)

> 
> -- 
> With Best Regards,
> Andy Shevchenko
> 
>