On Tue, Feb 07, 2023 at 07:09:41PM +0800, Kaihao Bai wrote:re-check and find that "TLB maintenance must be performed based on the size of the underlying translation table entries, to avoid TLB
In arm64, contiguous flag refers to the same TLB entry that shared by a
contiguous address range. If flush one entry of the address range, it
would cover the whole contiguous address range. Thus there's no need to
flush all contiguous range that CONT_PMD/PTE points to.
This doesn't work. The contiguous bit is a hint, so the CPU may not
coalesce multiple PTEs into a single TLB entry.
Sorry I misunderstood the underlying approach of contiguous bit. I