[irqchip: irq/irqchip-next] irqchip/aspeed-scu-ic: Correctly initialise status and enable registers
From: irqchip-bot for Ryan Chen
Date: Sun Feb 05 2023 - 06:30:16 EST
The following commit has been merged into the irq/irqchip-next branch of irqchip:
Commit-ID: e740604232dc5c3097808f3e91fd02d9316010c5
Gitweb: https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms/e740604232dc5c3097808f3e91fd02d9316010c5
Author: Ryan Chen <ryan_chen@xxxxxxxxxxxxxx>
AuthorDate: Mon, 30 Jan 2023 16:54:30 +08:00
Committer: Marc Zyngier <maz@xxxxxxxxxx>
CommitterDate: Sun, 05 Feb 2023 10:55:19
irqchip/aspeed-scu-ic: Correctly initialise status and enable registers
The status and enable registers are never initialised with sensible
default values. Fix those.
Signed-off-by: Ryan Chen <ryan_chen@xxxxxxxxxxxxxx>
[maz: commit message]
Signed-off-by: Marc Zyngier <maz@xxxxxxxxxx>
Link: https://lore.kernel.org/r/20230130085430.635583-1-ryan_chen@xxxxxxxxxxxxxx
---
drivers/irqchip/irq-aspeed-scu-ic.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/irqchip/irq-aspeed-scu-ic.c b/drivers/irqchip/irq-aspeed-scu-ic.c
index 279e92c..94a7223 100644
--- a/drivers/irqchip/irq-aspeed-scu-ic.c
+++ b/drivers/irqchip/irq-aspeed-scu-ic.c
@@ -17,8 +17,9 @@
#define ASPEED_SCU_IC_REG 0x018
#define ASPEED_SCU_IC_SHIFT 0
-#define ASPEED_SCU_IC_ENABLE GENMASK(6, ASPEED_SCU_IC_SHIFT)
+#define ASPEED_SCU_IC_ENABLE GENMASK(15, ASPEED_SCU_IC_SHIFT)
#define ASPEED_SCU_IC_NUM_IRQS 7
+#define ASPEED_SCU_IC_STATUS GENMASK(28, 16)
#define ASPEED_SCU_IC_STATUS_SHIFT 16
#define ASPEED_AST2600_SCU_IC0_REG 0x560
@@ -155,6 +156,8 @@ static int aspeed_scu_ic_of_init_common(struct aspeed_scu_ic *scu_ic,
rc = PTR_ERR(scu_ic->scu);
goto err;
}
+ regmap_write_bits(scu_ic->scu, scu_ic->reg, ASPEED_SCU_IC_STATUS, ASPEED_SCU_IC_STATUS);
+ regmap_write_bits(scu_ic->scu, scu_ic->reg, ASPEED_SCU_IC_ENABLE, 0);
irq = irq_of_parse_and_map(node, 0);
if (!irq) {