Re: [PATCH v8 1/4] dt-bindings: imx6q-pcie: Restruct i.MX PCIe schema

[Rob Herring]

On Wed, Feb 01, 2023 at 04:06:50PM +0800, Richard Zhu wrote:
> Restruct i.MX PCIe schema, derive the common properties, thus they can
> be shared by both the RC and Endpoint schema.
> 
> Update the description of fsl,imx6q-pcie.yaml, and move the EP mode
> compatible to fsl,imx6q-pcie-ep.yaml.
> 
> Add support for i.MX8M PCIe Endpoint modes, and update the MAINTAINER
> accordingly.
> 
> Signed-off-by: Richard Zhu <hongxing.zhu@xxxxxxx>
> ---
>  .../bindings/pci/fsl,imx6q-pcie-common.yaml   | 121 ++++++++++
>  .../bindings/pci/fsl,imx6q-pcie-ep.yaml       | 217 ++++++++++++++++++
>  .../bindings/pci/fsl,imx6q-pcie.yaml          | 111 +--------
>  MAINTAINERS                                   |   2 +
>  4 files changed, 347 insertions(+), 104 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-common.yaml
>  create mode 100644 Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml
> 
> diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-common.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-common.yaml
> new file mode 100644
> index 000000000000..a2eb56de0294
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-common.yaml
> @@ -0,0 +1,121 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pci/fsl,imx6q-pcie-common.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Freescale i.MX6 PCIe RC/EP controller
> +
> +maintainers:
> +  - Lucas Stach <l.stach@xxxxxxxxxxxxxx>
> +  - Richard Zhu <hongxing.zhu@xxxxxxx>
> +
> +description:
> +  Generic Freescale i.MX PCIe Root Port and Endpoint controller
> +  properties.
> +
> +properties:
> +  clocks:
> +    minItems: 3
> +    items:
> +      - description: PCIe bridge clock.
> +      - description: PCIe bus clock.
> +      - description: PCIe PHY clock.
> +      - description: Additional required clock entry for imx6sx-pcie,
> +          imx8mq-pcie.
> +
> +  clock-names:
> +    minItems: 3
> +    items:
> +      - const: pcie
> +      - const: pcie_bus
> +      - enum: [ pcie_phy, pcie_aux ]
> +      - enum: [ pcie_inbound_axi, pcie_aux ]
> +
> +  num-lanes:
> +    const: 1
> +
> +  fsl,imx7d-pcie-phy:
> +    $ref: /schemas/types.yaml#/definitions/phandle
> +    description: A phandle to an fsl,imx7d-pcie-phy node. Additional
> +      required properties for imx7d-pcie and imx8mq-pcie.
> +
> +  power-domains:
> +    minItems: 1
> +    items:
> +      - description: The phandle pointing to the DISPLAY domain for
> +          imx6sx-pcie, to PCIE_PHY power domain for imx7d-pcie and
> +          imx8mq-pcie.
> +      - description: The phandle pointing to the PCIE_PHY power domains
> +          for imx6sx-pcie.
> +
> +  power-domain-names:
> +    minItems: 1
> +    items:
> +      - const: pcie
> +      - const: pcie_phy
> +
> +  resets:
> +    minItems: 2
> +    maxItems: 3
> +    description: Phandles to PCIe-related reset lines exposed by SRC
> +      IP block. Additional required by imx7d-pcie and imx8mq-pcie.
> +
> +  reset-names:
> +    minItems: 2
> +    maxItems: 3
> +
> +  fsl,tx-deemph-gen1:
> +    description: Gen1 De-emphasis value (optional required).
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    default: 0
> +
> +  fsl,tx-deemph-gen2-3p5db:
> +    description: Gen2 (3.5db) De-emphasis value (optional required).
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    default: 0
> +
> +  fsl,tx-deemph-gen2-6db:
> +    description: Gen2 (6db) De-emphasis value (optional required).
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    default: 20
> +
> +  fsl,tx-swing-full:
> +    description: Gen2 TX SWING FULL value (optional required).
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    default: 127
> +
> +  fsl,tx-swing-low:
> +    description: TX launch amplitude swing_low value (optional required).
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    default: 127
> +
> +  fsl,max-link-speed:
> +    description: Specify PCI Gen for link capability (optional required).
> +      Note that the IMX6 LVDS clock outputs do not meet gen2 jitter
> +      requirements and thus for gen2 capability a gen2 compliant clock
> +      generator should be used and configured.
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    enum: [1, 2, 3, 4]
> +    default: 1
> +
> +  phys:
> +    maxItems: 1
> +
> +  phy-names:
> +    const: pcie-phy
> +
> +  vpcie-supply:
> +    description: Should specify the regulator in charge of PCIe port power.
> +      The regulator will be enabled when initializing the PCIe host and
> +      disabled either as part of the init process or when shutting down
> +      the host (optional required).
> +
> +  vph-supply:
> +    description: Should specify the regulator in charge of VPH one of
> +      the three PCIe PHY powers. This regulator can be supplied by both
> +      1.8v and 3.3v voltage supplies (optional required).
> +
> +additionalProperties: true
> +
> +...
> diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml
> new file mode 100644
> index 000000000000..8b2506a85083
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml
> @@ -0,0 +1,217 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pci/fsl,imx6q-pcie-ep.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Freescale i.MX6 PCIe Endpoint controller
> +
> +maintainers:
> +  - Lucas Stach <l.stach@xxxxxxxxxxxxxx>
> +  - Richard Zhu <hongxing.zhu@xxxxxxx>
> +
> +description: |+
> +  This PCIe controller is based on the Synopsys DesignWare PCIe IP and
> +  thus inherits all the common properties defined in snps,dw-pcie-ep.yaml.
> +  The controller instances are dual mode where in they can work either in
> +  Root Port mode or Endpoint mode but one at a time.
> +
> +properties:
> +  compatible:
> +    enum:
> +      - fsl,imx8mm-pcie-ep
> +      - fsl,imx8mq-pcie-ep
> +      - fsl,imx8mp-pcie-ep
> +
> +  reg:
> +    minItems: 2
> +
> +  reg-names:
> +    items:
> +      - const: dbi
> +      - const: addr_space
> +
> +  interrupts:
> +    items:
> +      - description: builtin eDMA interrupter.
> +
> +  interrupt-names:
> +    items:
> +      - const: dma
> +
> +required:
> +  - compatible
> +  - reg
> +  - reg-names
> +  - num-lanes
> +  - interrupts
> +  - interrupt-names
> +  - clocks
> +  - clock-names
> +
> +allOf:
> +  - $ref: /schemas/pci/snps,dw-pcie-ep.yaml#
> +  - $ref: /schemas/pci/fsl,imx6q-pcie-common.yaml#
> +
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            const: fsl,imx6sx-pcie-ep
> +    then:
> +      properties:
> +        clock-names:
> +          items:
> +            - {}
> +            - {}
> +            - const: pcie_phy
> +            - const: pcie_inbound_axi
> +        power-domains:
> +          minItems: 2
> +        power-domain-names:
> +          minItems: 2
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            const: fsl,imx8mq-pcie-ep
> +    then:
> +      properties:
> +        clock-names:
> +          items:
> +            - {}
> +            - {}
> +            - const: pcie_phy
> +            - const: pcie_aux
> +  - if:
> +      properties:
> +        compatible:
> +          not:
> +            contains:
> +              enum:
> +                - fsl,imx6sx-pcie-ep
> +                - fsl,imx8mq-pcie-ep
> +    then:
> +      properties:
> +        clocks:
> +          maxItems: 3
> +        clock-names:
> +          maxItems: 3
> +
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            enum:
> +              - fsl,imx6q-pcie-ep
> +              - fsl,imx6qp-pcie-ep
> +              - fsl,imx7d-pcie-ep
> +    then:
> +      properties:
> +        clock-names:
> +          maxItems: 3
> +          contains:
> +            const: pcie_phy
> +
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            enum:
> +              - fsl,imx8mm-pcie-ep
> +              - fsl,imx8mp-pcie-ep
> +    then:
> +      properties:
> +        clock-names:
> +          maxItems: 3
> +          contains:
> +            const: pcie_aux
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            enum:
> +              - fsl,imx6q-pcie-ep
> +              - fsl,imx6qp-pcie-ep
> +    then:
> +      properties:
> +        power-domains: false
> +        power-domain-names: false
> +
> +  - if:
> +      not:
> +        properties:
> +          compatible:
> +            contains:
> +              enum:
> +                - fsl,imx6sx-pcie-ep
> +                - fsl,imx6q-pcie-ep
> +                - fsl,imx6qp-pcie-ep
> +    then:
> +      properties:
> +        power-domains:
> +          maxItems: 1
> +        power-domain-names: false
> +
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            enum:
> +              - fsl,imx6q-pcie-ep
> +              - fsl,imx6sx-pcie-ep
> +              - fsl,imx6qp-pcie-ep
> +              - fsl,imx7d-pcie-ep
> +              - fsl,imx8mq-pcie-ep
> +    then:
> +      properties:
> +        resets:
> +          minItems: 3
> +        reset-names:
> +          items:
> +            - const: pciephy
> +            - const: apps
> +            - const: turnoff
> +    else:
> +      properties:
> +        resets:
> +          maxItems: 2
> +        reset-names:
> +          items:
> +            - const: apps
> +            - const: turnoff

All these constraints should be the same regardless of host or endpoint 
mode, so they belong in the common schema. After all, it's the same h/w 
for each SoC.

Rob