[PATCH v4 01/10] dt-bindings: qcom,*-geni: move #{address,size}-cells on i2c/spi nodes

From: Brian Masney
Date: Tue Jan 03 2023 - 13:24:39 EST


Move the #address-cells and #size-cells properties on the existing
i2c/spi example nodes below the reg property so that all of the
address-related properties are grouped together.

Signed-off-by: Brian Masney <bmasney@xxxxxxxxxx>
Link: https://lore.kernel.org/lkml/Y6Wnh+tXPhF6aC1b@xxxxxxxxxxxxxxxxxxxx/
---
New patch introduced in v4

.../devicetree/bindings/i2c/qcom,i2c-geni-qcom.yaml | 4 ++--
.../devicetree/bindings/soc/qcom/qcom,geni-se.yaml | 4 ++--
.../devicetree/bindings/spi/qcom,spi-geni-qcom.yaml | 8 ++++----
3 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/Documentation/devicetree/bindings/i2c/qcom,i2c-geni-qcom.yaml b/Documentation/devicetree/bindings/i2c/qcom,i2c-geni-qcom.yaml
index f5f7dc8f325c..594bf810a4aa 100644
--- a/Documentation/devicetree/bindings/i2c/qcom,i2c-geni-qcom.yaml
+++ b/Documentation/devicetree/bindings/i2c/qcom,i2c-geni-qcom.yaml
@@ -127,13 +127,13 @@ examples:
i2c@88000 {
compatible = "qcom,geni-i2c";
reg = <0x00880000 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c0_default>;
interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
<&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml
index ab4df0205285..d6128fb7d361 100644
--- a/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml
+++ b/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml
@@ -137,14 +137,14 @@ examples:
i2c0: i2c@a94000 {
compatible = "qcom,geni-i2c";
reg = <0 0xa94000 0 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qup_1_i2c_5_active>;
pinctrl-1 = <&qup_1_i2c_5_sleep>;
- #address-cells = <1>;
- #size-cells = <0>;
};

uart0: serial@a88000 {
diff --git a/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.yaml b/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.yaml
index 2e20ca313ec1..efa7f52941f8 100644
--- a/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.yaml
+++ b/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.yaml
@@ -85,13 +85,13 @@ examples:
spi@880000 {
compatible = "qcom,geni-spi";
reg = <0x00880000 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_spi0_default>;
interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
power-domains = <&rpmhpd SC7180_CX>;
operating-points-v2 = <&qup_opp_table>;
interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
@@ -105,6 +105,8 @@ examples:
spi@884000 {
compatible = "qcom,geni-spi";
reg = <0x00884000 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
@@ -113,6 +115,4 @@ examples:
pinctrl-names = "default";
pinctrl-0 = <&qup_spi1_default>;
interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
};
--
2.39.0