Re: [PATCH v3 4/7] arm64: dts: qcom: sc8280xp: add missing i2c nodes

[Konrad Dybcio]

On 23.12.2022 11:37, Johan Hovold wrote:
> On Tue, Dec 20, 2022 at 02:28:51PM -0500, Brian Masney wrote:
>> Add the missing nodes for the i2c buses that's present on this SoC.
>>
>> This work was derived from various patches that Qualcomm delivered
>> to Red Hat in a downstream kernel.
>>
>> Signed-off-by: Brian Masney <bmasney@xxxxxxxxxx>
>> ---
>> Changes from v2 to v3
>> - None
>>
>> Changes from v1 to v2
>> - Dropped qupX_ prefix from labels. (Johan)
>>
>>  arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 352 +++++++++++++++++++++++++
>>  1 file changed, 352 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
>> index f1111cd7f679..a502d4e19d98 100644
>> --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
>> @@ -813,6 +813,38 @@ qup2: geniqup@8c0000 {
>>  
>>  			status = "disabled";
>>  
>> +			i2c16: i2c@880000 {
>> +				compatible = "qcom,geni-i2c";
>> +				reg = <0 0x00880000 0 0x4000>;
>> +				clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
>> +				clock-names = "se";
>> +				interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
>> +				#address-cells = <1>;
>> +				#size-cells = <0>;
> 
> I'm aware that the two current i2c nodes has these two properties here
> in the middle, but would you mind moving '#address-cells' and
> '#size-cells' after 'reg' instead where I'd expect them to be?
Hm.. we've been sticking them somewhere near the end for the longest
time for every bus-like, or generally "i have childen" type node..
I see it's a rather mixed bag in non-qcom SoCs, people just seem to
put it wherever they please.. The dt spec doesn't seem to mention any
preference fwiw.

Konrad
> 
> Same for the spi patch.
> 
> I can clean up the existing two nodes (and binding example) unless you
> want to do it.
> 
>> +				power-domains = <&rpmhpd SC8280XP_CX>;
>> +				interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
>> +				                <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
>> +				                <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
>> +				interconnect-names = "qup-core", "qup-config", "qup-memory";
>> +				status = "disabled";
>> +			};
> 
> Johan