Re: [PATCH v3 1/5] cacheinfo: Use RISC-V's init_cache_level() as generic OF implementation

[Pierre Gondois]

Hello Rob,

On 12/21/22 00:39, Rob Herring wrote:
> On Fri, Dec 09, 2022 at 11:31:23AM +0100, Pierre Gondois wrote:
> > RISC-V's implementation of init_of_cache_level() is following
> > the Devicetree Specification v0.3 regarding caches, cf.:
> > - s3.7.3 'Internal (L1) Cache Properties'
> > - s3.8 'Multi-level and Shared Cache Nodes'
> >
> > Allow reusing the implementation by moving it.
> >
> > Signed-off-by: Pierre Gondois <pierre.gondois@xxxxxxx>
> > Reviewed-by: Conor Dooley <conor.dooley@xxxxxxxxxxxxx>
> > Reviewed-by: Sudeep Holla <sudeep.holla@xxxxxxx>
> > Acked-by: Palmer Dabbelt <palmer@xxxxxxxxxxxx>
> > ---
> >   arch/riscv/kernel/cacheinfo.c | 39 +------------------------------
> >   drivers/base/cacheinfo.c      | 44 +++++++++++++++++++++++++++++++++++
> >   include/linux/cacheinfo.h     |  1 +
> >   3 files changed, 46 insertions(+), 38 deletions(-)
> >
> > diff --git a/arch/riscv/kernel/cacheinfo.c b/arch/riscv/kernel/cacheinfo.c
> > index 90deabfe63ea..440a3df5944c 100644
> > --- a/arch/riscv/kernel/cacheinfo.c
> > +++ b/arch/riscv/kernel/cacheinfo.c
> > @@ -115,44 +115,7 @@ static void fill_cacheinfo(struct cacheinfo **this_leaf,
> >   
> >   int init_cache_level(unsigned int cpu)
> >   {
> > -	struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu);
> > -	struct device_node *np = of_cpu_device_node_get(cpu);
> > -	struct device_node *prev = NULL;
> > -	int levels = 0, leaves = 0, level;
> > -
> > -	if (of_property_read_bool(np, "cache-size"))
> > -		++leaves;
> > -	if (of_property_read_bool(np, "i-cache-size"))
> > -		++leaves;
> > -	if (of_property_read_bool(np, "d-cache-size"))
> > -		++leaves;
> > -	if (leaves > 0)
> > -		levels = 1;
> > -
> > -	prev = np;
> > -	while ((np = of_find_next_cache_node(np))) {
> > -		of_node_put(prev);
> > -		prev = np;
> > -		if (!of_device_is_compatible(np, "cache"))
> > -			break;
> > -		if (of_property_read_u32(np, "cache-level", &level))
> > -			break;
> > -		if (level <= levels)
> > -			break;
> > -		if (of_property_read_bool(np, "cache-size"))
> > -			++leaves;
> > -		if (of_property_read_bool(np, "i-cache-size"))
> > -			++leaves;
> > -		if (of_property_read_bool(np, "d-cache-size"))
> > -			++leaves;
> > -		levels = level;
> > -	}
> > -
> > -	of_node_put(np);
> > -	this_cpu_ci->num_levels = levels;
> > -	this_cpu_ci->num_leaves = leaves;
> > -
> > -	return 0;
> > +	return init_of_cache_level(cpu);
>
> Not in this patch, but in patch 5, shouldn't riscv init_cache_level() be
> removed? The topology code already called init_of_cache_level() and
> RiscV has nothing architectural to add/change. IOW, init_cache_level()
> should only do architecture defined init, and not anything DT or ACPI
> related (unless those are non-standard).
>
> Rob

I think you are right. Just to re-phrase your point:
init_of_cache_level() is called through this path:
init_cpu_topology()
\-fetch_cache_info()
  \-init_of_cache_level()

If there is missing information in the DT and it's not possible to create the
cacheinfo, then the arch specific implementation i.e. init_cache_level() is
called through:
update_siblings_masks() | cacheinfo_cpu_online()
\-detect_cache_attributes()
  \-init_cache_level()

This is useful for arm to call init_cache_level() since it is possible
to extract some information from some registers. For RISC-V, if
init_of_cache_level() fails, then init_cache_level() will fail again.
So removing RISC-V's init_cache_level() makes sense.

Regards,
Pierre