RE: [PATCH 2/4] soc: mediatek: pm-domains: Add ADSP power domain data for MT8192

[Allen-KH Cheng (程冠勳)]

Hi Matthias,

Thanks for the reminder. I will check this and resend next version.

Best Regards,
Allen


-----Original Message-----
From: Matthias Brugger <matthias.bgg@xxxxxxxxx> 
Sent: Friday, December 16, 2022 7:16 PM
To: Allen-KH Cheng (程冠勳) <Allen-KH.Cheng@xxxxxxxxxxxx>; Rob Herring <
robh+dt@xxxxxxxxxx>; Krzysztof Kozlowski <
krzysztof.kozlowski+dt@xxxxxxxxxx>; Chun-Jie Chen (陳浚桀) <
Chun-Jie.Chen@xxxxxxxxxxxx>; Stephen Boyd <sboyd@xxxxxxxxxx>; Ikjoon
Jang <ikjn@xxxxxxxxxxxx>
Cc: Project_Global_Chrome_Upstream_Group <
Project_Global_Chrome_Upstream_Group@xxxxxxxxxxxx>; 
angelogioacchino.delregno@xxxxxxxxxxxxx; devicetree@xxxxxxxxxxxxxxx; 
linux-arm-kernel@xxxxxxxxxxxxxxxxxxx; linux-kernel@xxxxxxxxxxxxxxx; 
linux-mediatek@xxxxxxxxxxxxxxxxxxx; Chen-Yu Tsai <wenst@xxxxxxxxxxxx>
Subject: Re: [PATCH 2/4] soc: mediatek: pm-domains: Add ADSP power
domain data for MT8192



On 15/12/2022 13:00, Allen-KH Cheng wrote:
> Add ADSP pm-domains (mtcmos) data for MT8192 SoC.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@xxxxxxxxxxxx>
> ---
>   drivers/soc/mediatek/mt8192-pm-domains.h | 16 ++++++++++++++++
>   1 file changed, 16 insertions(+)
> 
> diff --git a/drivers/soc/mediatek/mt8192-pm-domains.h
> b/drivers/soc/mediatek/mt8192-pm-domains.h
> index b97b2051920f..19e58f0ca1df 100644
> --- a/drivers/soc/mediatek/mt8192-pm-domains.h
> +++ b/drivers/soc/mediatek/mt8192-pm-domains.h
> @@ -287,6 +287,22 @@ static const struct scpsys_domain_data
> scpsys_domain_data_mt8192[] = {
>   		.sram_pdn_bits = GENMASK(8, 8),
>   		.sram_pdn_ack_bits = GENMASK(12, 12),
>   	},
> +	[MT8192_POWER_DOMAIN_ADSP] = {
> +		.name = "adsp",
> +		.sta_mask = BIT(22),
> +		.ctl_offs = 0x0358,
> +		.sram_pdn_bits = GENMASK(8, 8),
> +		.sram_pdn_ack_bits = GENMASK(12, 12),
> +		.ext_buck_iso_offs = 0x039C,
> +		.ext_buck_iso_mask = BIT(2),

Not defined in upstream. It seems we are missing something here.

Regards,
Matthias

> +		.bp_infracfg = {
> +			BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_2_ADSP,
> +				    MT8192_TOP_AXI_PROT_EN_2_SET,
> +				    MT8192_TOP_AXI_PROT_EN_2_CLR,
> +				    MT8192_TOP_AXI_PROT_EN_2_STA1),
> +		},
> +		.caps = MTK_SCPD_SRAM_ISO | MTK_SCPD_EXT_BUCK_ISO,
> +	},
>   	[MT8192_POWER_DOMAIN_CAM] = {
>   		.name = "cam",
>   		.sta_mask = BIT(23),