Re: [PATCH v2 2/6] arm64: dts: qcom: sdm845: order top-level nodes alphabetically

From: Dmitry Baryshkov
Date: Mon Dec 12 2022 - 08:48:15 EST

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On 12 December 2022 13:02:28 GMT+03:00, Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx> wrote:
>Order top-level nodes like memory, reserved-memory, opp-table-cpu
>alphabetically for easier code maintenance. No functional change (same
>dtx_diff, except phandle changes).
>
>Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx>

Reviewed-by: Dmitry Baryshkov<dmitry.baryshkov@xxxxxxxxxx>

>
>---
>
>Changes since v1:
>1. New patch
>---
> arch/arm64/boot/dts/qcom/sdm845.dtsi | 384 +++++++++++++--------------
> 1 file changed, 192 insertions(+), 192 deletions(-)
>
>diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
>index a63dbd12230f..88e7d4061aae 100644
>--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
>+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
>@@ -69,122 +69,18 @@ aliases {
>
> chosen { };
>
>- memory@80000000 {
>- device_type = "memory";
>- /* We expect the bootloader to fill in the size */
>- reg = <0 0x80000000 0 0>;
>- };
>-
>- reserved-memory {
>- #address-cells = <2>;
>- #size-cells = <2>;
>- ranges;
>-
>- hyp_mem: hyp-mem@85700000 {
>- reg = <0 0x85700000 0 0x600000>;
>- no-map;
>- };
>-
>- xbl_mem: xbl-mem@85e00000 {
>- reg = <0 0x85e00000 0 0x100000>;
>- no-map;
>- };
>-
>- aop_mem: aop-mem@85fc0000 {
>- reg = <0 0x85fc0000 0 0x20000>;
>- no-map;
>- };
>-
>- aop_cmd_db_mem: aop-cmd-db-mem@85fe0000 {
>- compatible = "qcom,cmd-db";
>- reg = <0x0 0x85fe0000 0 0x20000>;
>- no-map;
>- };
>-
>- smem@86000000 {
>- compatible = "qcom,smem";
>- reg = <0x0 0x86000000 0 0x200000>;
>- no-map;
>- hwlocks = <&tcsr_mutex 3>;
>- };
>-
>- tz_mem: tz@86200000 {
>- reg = <0 0x86200000 0 0x2d00000>;
>- no-map;
>- };
>-
>- rmtfs_mem: rmtfs@88f00000 {
>- compatible = "qcom,rmtfs-mem";
>- reg = <0 0x88f00000 0 0x200000>;
>- no-map;
>-
>- qcom,client-id = <1>;
>- qcom,vmid = <15>;
>- };
>-
>- qseecom_mem: qseecom@8ab00000 {
>- reg = <0 0x8ab00000 0 0x1400000>;
>- no-map;
>- };
>-
>- camera_mem: camera-mem@8bf00000 {
>- reg = <0 0x8bf00000 0 0x500000>;
>- no-map;
>- };
>-
>- ipa_fw_mem: ipa-fw@8c400000 {
>- reg = <0 0x8c400000 0 0x10000>;
>- no-map;
>- };
>-
>- ipa_gsi_mem: ipa-gsi@8c410000 {
>- reg = <0 0x8c410000 0 0x5000>;
>- no-map;
>- };
>-
>- gpu_mem: gpu@8c415000 {
>- reg = <0 0x8c415000 0 0x2000>;
>- no-map;
>- };
>-
>- adsp_mem: adsp@8c500000 {
>- reg = <0 0x8c500000 0 0x1a00000>;
>- no-map;
>- };
>-
>- wlan_msa_mem: wlan-msa@8df00000 {
>- reg = <0 0x8df00000 0 0x100000>;
>- no-map;
>- };
>-
>- mpss_region: mpss@8e000000 {
>- reg = <0 0x8e000000 0 0x7800000>;
>- no-map;
>- };
>-
>- venus_mem: venus@95800000 {
>- reg = <0 0x95800000 0 0x500000>;
>- no-map;
>- };
>-
>- cdsp_mem: cdsp@95d00000 {
>- reg = <0 0x95d00000 0 0x800000>;
>- no-map;
>- };
>-
>- mba_region: mba@96500000 {
>- reg = <0 0x96500000 0 0x200000>;
>- no-map;
>- };
>-
>- slpi_mem: slpi@96700000 {
>- reg = <0 0x96700000 0 0x1400000>;
>- no-map;
>+ clocks {
>+ xo_board: xo-board {
>+ compatible = "fixed-clock";
>+ #clock-cells = <0>;
>+ clock-frequency = <38400000>;
>+ clock-output-names = "xo_board";
> };
>
>- spss_mem: spss@97b00000 {
>- reg = <0 0x97b00000 0 0x100000>;
>- no-map;
>+ sleep_clk: sleep-clk {
>+ compatible = "fixed-clock";
>+ #clock-cells = <0>;
>+ clock-frequency = <32764>;
> };
> };
>
>@@ -436,6 +332,18 @@ CLUSTER_SLEEP_0: cluster-sleep-0 {
> };
> };
>
>+ firmware {
>+ scm {
>+ compatible = "qcom,scm-sdm845", "qcom,scm";
>+ };
>+ };
>+
>+ memory@80000000 {
>+ device_type = "memory";
>+ /* We expect the bootloader to fill in the size */
>+ reg = <0 0x80000000 0 0>;
>+ };
>+
> cpu0_opp_table: opp-table-cpu0 {
> compatible = "operating-points-v2";
> opp-shared;
>@@ -701,32 +609,174 @@ pmu {
> interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
> };
>
>- timer {
>- compatible = "arm,armv8-timer";
>- interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
>- <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
>- <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
>- <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
>- };
>+ psci: psci {
>+ compatible = "arm,psci-1.0";
>+ method = "smc";
>
>- clocks {
>- xo_board: xo-board {
>- compatible = "fixed-clock";
>- #clock-cells = <0>;
>- clock-frequency = <38400000>;
>- clock-output-names = "xo_board";
>+ CPU_PD0: power-domain-cpu0 {
>+ #power-domain-cells = <0>;
>+ power-domains = <&CLUSTER_PD>;
>+ domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
> };
>
>- sleep_clk: sleep-clk {
>- compatible = "fixed-clock";
>- #clock-cells = <0>;
>- clock-frequency = <32764>;
>+ CPU_PD1: power-domain-cpu1 {
>+ #power-domain-cells = <0>;
>+ power-domains = <&CLUSTER_PD>;
>+ domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
>+ };
>+
>+ CPU_PD2: power-domain-cpu2 {
>+ #power-domain-cells = <0>;
>+ power-domains = <&CLUSTER_PD>;
>+ domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
>+ };
>+
>+ CPU_PD3: power-domain-cpu3 {
>+ #power-domain-cells = <0>;
>+ power-domains = <&CLUSTER_PD>;
>+ domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
>+ };
>+
>+ CPU_PD4: power-domain-cpu4 {
>+ #power-domain-cells = <0>;
>+ power-domains = <&CLUSTER_PD>;
>+ domain-idle-states = <&BIG_CPU_SLEEP_0>;
>+ };
>+
>+ CPU_PD5: power-domain-cpu5 {
>+ #power-domain-cells = <0>;
>+ power-domains = <&CLUSTER_PD>;
>+ domain-idle-states = <&BIG_CPU_SLEEP_0>;
>+ };
>+
>+ CPU_PD6: power-domain-cpu6 {
>+ #power-domain-cells = <0>;
>+ power-domains = <&CLUSTER_PD>;
>+ domain-idle-states = <&BIG_CPU_SLEEP_0>;
>+ };
>+
>+ CPU_PD7: power-domain-cpu7 {
>+ #power-domain-cells = <0>;
>+ power-domains = <&CLUSTER_PD>;
>+ domain-idle-states = <&BIG_CPU_SLEEP_0>;
>+ };
>+
>+ CLUSTER_PD: power-domain-cluster {
>+ #power-domain-cells = <0>;
>+ domain-idle-states = <&CLUSTER_SLEEP_0>;
> };
> };
>
>- firmware {
>- scm {
>- compatible = "qcom,scm-sdm845", "qcom,scm";
>+ reserved-memory {
>+ #address-cells = <2>;
>+ #size-cells = <2>;
>+ ranges;
>+
>+ hyp_mem: hyp-mem@85700000 {
>+ reg = <0 0x85700000 0 0x600000>;
>+ no-map;
>+ };
>+
>+ xbl_mem: xbl-mem@85e00000 {
>+ reg = <0 0x85e00000 0 0x100000>;
>+ no-map;
>+ };
>+
>+ aop_mem: aop-mem@85fc0000 {
>+ reg = <0 0x85fc0000 0 0x20000>;
>+ no-map;
>+ };
>+
>+ aop_cmd_db_mem: aop-cmd-db-mem@85fe0000 {
>+ compatible = "qcom,cmd-db";
>+ reg = <0x0 0x85fe0000 0 0x20000>;
>+ no-map;
>+ };
>+
>+ smem@86000000 {
>+ compatible = "qcom,smem";
>+ reg = <0x0 0x86000000 0 0x200000>;
>+ no-map;
>+ hwlocks = <&tcsr_mutex 3>;
>+ };
>+
>+ tz_mem: tz@86200000 {
>+ reg = <0 0x86200000 0 0x2d00000>;
>+ no-map;
>+ };
>+
>+ rmtfs_mem: rmtfs@88f00000 {
>+ compatible = "qcom,rmtfs-mem";
>+ reg = <0 0x88f00000 0 0x200000>;
>+ no-map;
>+
>+ qcom,client-id = <1>;
>+ qcom,vmid = <15>;
>+ };
>+
>+ qseecom_mem: qseecom@8ab00000 {
>+ reg = <0 0x8ab00000 0 0x1400000>;
>+ no-map;
>+ };
>+
>+ camera_mem: camera-mem@8bf00000 {
>+ reg = <0 0x8bf00000 0 0x500000>;
>+ no-map;
>+ };
>+
>+ ipa_fw_mem: ipa-fw@8c400000 {
>+ reg = <0 0x8c400000 0 0x10000>;
>+ no-map;
>+ };
>+
>+ ipa_gsi_mem: ipa-gsi@8c410000 {
>+ reg = <0 0x8c410000 0 0x5000>;
>+ no-map;
>+ };
>+
>+ gpu_mem: gpu@8c415000 {
>+ reg = <0 0x8c415000 0 0x2000>;
>+ no-map;
>+ };
>+
>+ adsp_mem: adsp@8c500000 {
>+ reg = <0 0x8c500000 0 0x1a00000>;
>+ no-map;
>+ };
>+
>+ wlan_msa_mem: wlan-msa@8df00000 {
>+ reg = <0 0x8df00000 0 0x100000>;
>+ no-map;
>+ };
>+
>+ mpss_region: mpss@8e000000 {
>+ reg = <0 0x8e000000 0 0x7800000>;
>+ no-map;
>+ };
>+
>+ venus_mem: venus@95800000 {
>+ reg = <0 0x95800000 0 0x500000>;
>+ no-map;
>+ };
>+
>+ cdsp_mem: cdsp@95d00000 {
>+ reg = <0 0x95d00000 0 0x800000>;
>+ no-map;
>+ };
>+
>+ mba_region: mba@96500000 {
>+ reg = <0 0x96500000 0 0x200000>;
>+ no-map;
>+ };
>+
>+ slpi_mem: slpi@96700000 {
>+ reg = <0 0x96700000 0 0x1400000>;
>+ no-map;
>+ };
>+
>+ spss_mem: spss@97b00000 {
>+ reg = <0 0x97b00000 0 0x100000>;
>+ no-map;
> };
> };
>
>@@ -1018,64 +1068,6 @@ slpi_smp2p_in: slave-kernel {
> };
> };
>
>- psci: psci {
>- compatible = "arm,psci-1.0";
>- method = "smc";
>-
>- CPU_PD0: power-domain-cpu0 {
>- #power-domain-cells = <0>;
>- power-domains = <&CLUSTER_PD>;
>- domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
>- };
>-
>- CPU_PD1: power-domain-cpu1 {
>- #power-domain-cells = <0>;
>- power-domains = <&CLUSTER_PD>;
>- domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
>- };
>-
>- CPU_PD2: power-domain-cpu2 {
>- #power-domain-cells = <0>;
>- power-domains = <&CLUSTER_PD>;
>- domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
>- };
>-
>- CPU_PD3: power-domain-cpu3 {
>- #power-domain-cells = <0>;
>- power-domains = <&CLUSTER_PD>;
>- domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
>- };
>-
>- CPU_PD4: power-domain-cpu4 {
>- #power-domain-cells = <0>;
>- power-domains = <&CLUSTER_PD>;
>- domain-idle-states = <&BIG_CPU_SLEEP_0>;
>- };
>-
>- CPU_PD5: power-domain-cpu5 {
>- #power-domain-cells = <0>;
>- power-domains = <&CLUSTER_PD>;
>- domain-idle-states = <&BIG_CPU_SLEEP_0>;
>- };
>-
>- CPU_PD6: power-domain-cpu6 {
>- #power-domain-cells = <0>;
>- power-domains = <&CLUSTER_PD>;
>- domain-idle-states = <&BIG_CPU_SLEEP_0>;
>- };
>-
>- CPU_PD7: power-domain-cpu7 {
>- #power-domain-cells = <0>;
>- power-domains = <&CLUSTER_PD>;
>- domain-idle-states = <&BIG_CPU_SLEEP_0>;
>- };
>-
>- CLUSTER_PD: power-domain-cluster {
>- #power-domain-cells = <0>;
>- domain-idle-states = <&CLUSTER_SLEEP_0>;
>- };
>- };
>-
> soc: soc@0 {
> #address-cells = <2>;
> #size-cells = <2>;
>@@ -5771,4 +5763,12 @@ modem_alert0: trip-point0 {
> };
> };
> };
>+
>+ timer {
>+ compatible = "arm,armv8-timer";
>+ interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
>+ <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
>+ <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
>+ <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
>+ };
> };

--
With best wishes
Dmitry

Next message: Dmitry Baryshkov: "Re: [PATCH v2 3/6] arm64: dts: qcom: sc7180: move QUP and QSPI opp tables out of SoC node"
Previous message: Dmitry Baryshkov: "Re: [PATCH v2 1/6] arm64: dts: qcom: sc7180: order top-level nodes alphabetically"
In reply to: Konrad Dybcio: "Re: [PATCH v2 2/6] arm64: dts: qcom: sdm845: order top-level nodes alphabetically"
Next in thread: Krzysztof Kozlowski: "[PATCH v2 3/6] arm64: dts: qcom: sc7180: move QUP and QSPI opp tables out of SoC node"
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