Re: [PATCH v3 11/12] riscv: Add the Allwinner SoC family Kconfig option

From: Conor Dooley
Date: Thu Dec 08 2022 - 04:12:28 EST


Acked-by: Conor Dooley <conor.dooley@xxxxxxxxxxxxx>

On 8 December 2022 10:02:36 GMT+01:00, Samuel Holland <samuel@xxxxxxxxxxxx> wrote:
>Allwinner manufactures the sunxi family of application processors. This
>includes the "sun8i" series of ARMv7 SoCs, the "sun50i" series of ARMv8
>SoCs, and now the "sun20i" series of 64-bit RISC-V SoCs.
>
>The first SoC in the sun20i series is D1, containing a single T-HEAD
>C906 core. D1s is a low-pin-count variant of D1 with co-packaged DRAM.
>
>Most peripherals are shared across the entire chip family. In fact, the
>ARMv7 T113 SoC is pin-compatible and almost entirely register-compatible
>with the D1s.
>
>This means many existing device drivers can be reused. To facilitate
>this reuse, name the symbol ARCH_SUNXI, since that is what the existing
>drivers have as their dependency.
>
>Acked-by: Palmer Dabbelt <palmer@xxxxxxxxxxxx>
>Reviewed-by: Guo Ren <guoren@xxxxxxxxxx>
>Reviewed-by: Heiko Stuebner <heiko@xxxxxxxxx>
>Tested-by: Heiko Stuebner <heiko@xxxxxxxxx>
>Signed-off-by: Samuel Holland <samuel@xxxxxxxxxxxx>
>---
>
>Changes in v3:
> - ARCH_SUNXI depends on MMU && !XIP_KERNEL
>
>Changes in v2:
> - Sort Kconfig as if we had done s/SOC_/ARCH_/ for future-proofing
>
> arch/riscv/Kconfig.socs | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
>diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
>index 69774bb362d6..f655dea86d69 100644
>--- a/arch/riscv/Kconfig.socs
>+++ b/arch/riscv/Kconfig.socs
>@@ -26,6 +26,16 @@ config SOC_STARFIVE
> help
> This enables support for StarFive SoC platform hardware.
>
>+config ARCH_SUNXI
>+ bool "Allwinner sun20i SoCs"
>+ depends on MMU && !XIP_KERNEL
>+ select ERRATA_THEAD
>+ select SIFIVE_PLIC
>+ select SUN4I_TIMER
>+ help
>+ This enables support for Allwinner sun20i platform hardware,
>+ including boards based on the D1 and D1s SoCs.
>+
> config SOC_VIRT
> bool "QEMU Virt Machine"
> select CLINT_TIMER if RISCV_M_MODE