[GIT PULL] MediaTek Clock Changes for 6.2

[Chen-Yu Tsai]

The following changes since commit 9abf2313adc1ca1b6180c508c25f22f9395cc780:

  Linux 6.1-rc1 (2022-10-16 15:36:24 -0700)

are available in the Git repository at:

  https://git.kernel.org/pub/scm/linux/kernel/git/wens/linux.git tags/mtk-clk-for-6.2

for you to fetch changes up to a46315295489933209e902638cd287aeb5f982ab:

  clk: mediatek: fix dependency of MT7986 ADC clocks (2022-11-29 14:49:29 +0800)

----------------------------------------------------------------
MediaTek clk driver changes for 6.2

Some more cleanup work, and a new driver for frequency hopping
controller hardware.

- Remove flags from univ/main/syspll child fixed factor clocks across
  MediaTek platforms
  - The idea is to not have the clk core try to reconfigure the system
    PLLs, i.e. have them be stable
- Fix clock dependency for ADC on MT7986
- New driver for frequency hopping controller hardware on MT8186
  - This does frequency hopping and spread spectrum clocks in hardware

----------------------------------------------------------------
AngeloGioacchino Del Regno (10):
      clk: mediatek: clk-mtk: Allow specifying flags on mtk_fixed_factor clocks
      clk: mediatek: mt8186-topckgen: Drop flags for main/univpll fixed factors
      clk: mediatek: mt8183: Compress top_divs array entries
      clk: mediatek: mt8183: Drop flags for sys/univpll fixed factors
      clk: mediatek: mt8173: Drop flags for main/sys/univpll fixed factors
      clk: mediatek: mt6795-topckgen: Drop flags for main/sys/univpll fixed factors
      clk: mediatek: mt8192: Drop flags for main/univpll fixed factors
      clk: mediatek: mt8195-topckgen: Drop flags for main/univpll fixed factors
      clk: mediatek: mt8186-mfg: Propagate rate changes to parent
      clk: mediatek: mt8186-topckgen: Add GPU clock mux notifier

Daniel Golle (1):
      clk: mediatek: fix dependency of MT7986 ADC clocks

Johnson Wang (4):
      clk: mediatek: Export PLL operations symbols
      dt-bindings: clock: mediatek: Add new bindings of MediaTek frequency hopping
      clk: mediatek: Add new clock driver to handle FHCTL hardware
      clk: mediatek: Change PLL register API for MT8186

 .../bindings/clock/mediatek,mt8186-fhctl.yaml      |  53 ++++
 drivers/clk/mediatek/Kconfig                       |   8 +
 drivers/clk/mediatek/Makefile                      |   1 +
 drivers/clk/mediatek/clk-fhctl.c                   | 244 ++++++++++++++++++
 drivers/clk/mediatek/clk-fhctl.h                   |  26 ++
 drivers/clk/mediatek/clk-mt6795-topckgen.c         |  76 +++---
 drivers/clk/mediatek/clk-mt7986-infracfg.c         |   2 +-
 drivers/clk/mediatek/clk-mt8173.c                  |  76 +++---
 drivers/clk/mediatek/clk-mt8183.c                  | 216 ++++++----------
 drivers/clk/mediatek/clk-mt8186-apmixedsys.c       |  66 ++++-
 drivers/clk/mediatek/clk-mt8186-mfg.c              |   5 +-
 drivers/clk/mediatek/clk-mt8186-topckgen.c         |  89 ++++---
 drivers/clk/mediatek/clk-mt8192.c                  |  76 +++---
 drivers/clk/mediatek/clk-mt8195-topckgen.c         |  78 +++---
 drivers/clk/mediatek/clk-mtk.c                     |   2 +-
 drivers/clk/mediatek/clk-mtk.h                     |   7 +-
 drivers/clk/mediatek/clk-pll.c                     |  84 +++----
 drivers/clk/mediatek/clk-pll.h                     |  55 +++++
 drivers/clk/mediatek/clk-pllfh.c                   | 275 +++++++++++++++++++++
 drivers/clk/mediatek/clk-pllfh.h                   |  82 ++++++
 20 files changed, 1135 insertions(+), 386 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt8186-fhctl.yaml
 create mode 100644 drivers/clk/mediatek/clk-fhctl.c
 create mode 100644 drivers/clk/mediatek/clk-fhctl.h
 create mode 100644 drivers/clk/mediatek/clk-pllfh.c
 create mode 100644 drivers/clk/mediatek/clk-pllfh.h