[PATCH 8/9] dt-bindings: clock: Add SM8550 TCSR CC clock bindings

[Abel Vesa]

Add bindings documentation for clock TCSR driver on SM8550.

Signed-off-by: Abel Vesa <abel.vesa@xxxxxxxxxx>
---
 .../bindings/clock/qcom,tcsrcc-sm8550.yaml    | 46 +++++++++++++++++++
 .../dt-bindings/clock/qcom,tcsrcc-sm8550.h    | 18 ++++++++
 2 files changed, 64 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/qcom,tcsrcc-sm8550.yaml
 create mode 100644 include/dt-bindings/clock/qcom,tcsrcc-sm8550.h

diff --git a/Documentation/devicetree/bindings/clock/qcom,tcsrcc-sm8550.yaml b/Documentation/devicetree/bindings/clock/qcom,tcsrcc-sm8550.yaml
new file mode 100644
index 000000000000..7d7bacb23610
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,tcsrcc-sm8550.yaml
@@ -0,0 +1,46 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,tcsrcc-sm8550.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm TCSR Clock Controller Binding for SM8550
+
+maintainers:
+  - Bjorn Andersson <andersson@xxxxxxxxxx>
+
+description: |
+  Qualcomm TCSR clock control module which supports the clocks,
+  resets and power domains on SM8550
+
+  See also:
+  - dt-bindings/clock/qcom,tcsrcc-sm8550.h
+
+properties:
+  compatible:
+    const: qcom,sm8550-tcsrcc
+
+  '#clock-cells':
+    const: 1
+
+  '#reset-cells':
+    const: 1
+
+  reg:
+    maxItems: 1
+
+required:
+  - compatible
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    clock-controller@1fc0000 {
+      compatible = "qcom,sm8550-tcsrcc";
+      reg = <0x1fc0000 0x30000>;
+      #clock-cells = <1>;
+      #reset-cells = <1>;
+    };
+
+...
diff --git a/include/dt-bindings/clock/qcom,tcsrcc-sm8550.h b/include/dt-bindings/clock/qcom,tcsrcc-sm8550.h
new file mode 100644
index 000000000000..eda360e84f0a
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,tcsrcc-sm8550.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2022, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022, Linaro Limited
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_TCSR_CC_SM8550_H
+#define _DT_BINDINGS_CLK_QCOM_TCSR_CC_SM8550_H
+
+/* GCC clocks */
+#define TCSR_PCIE_0_CLKREF_EN					0
+#define TCSR_PCIE_1_CLKREF_EN					1
+#define TCSR_UFS_CLKREF_EN					2
+#define TCSR_UFS_PAD_CLKREF_EN					3
+#define TCSR_USB2_CLKREF_EN					4
+#define TCSR_USB3_CLKREF_EN					5
+
+#endif
-- 
2.34.1