RE: [PATCH v1] soc: imx: imx8mp-blk-ctrl: Add PCIe SYSPLL configurations

[Hongxing Zhu]

> -----Original Message-----
> From: Hongxing Zhu
> Sent: 2022年11月2日 9:46
> To: Lucas Stach <l.stach@xxxxxxxxxxxxxx>; Shawn Guo <shawnguo@xxxxxxxxxx>
> Cc: marex@xxxxxxx; tharvey@xxxxxxxxxxxxx; vkoul@xxxxxxxxxx;
> bhelgaas@xxxxxxxxxx; lorenzo.pieralisi@xxxxxxx;
> alexander.stein@xxxxxxxxxxxxxxx; richard.leitner@xxxxxxxxx;
> devicetree@xxxxxxxxxxxxxxx; linux-pci@xxxxxxxxxxxxxxx;
> linux-arm-kernel@xxxxxxxxxxxxxxxxxxx; linux-kernel@xxxxxxxxxxxxxxx;
> kernel@xxxxxxxxxxxxxx; dl-linux-imx <linux-imx@xxxxxxx>;
> marcel.ziswiler@xxxxxxxxxxx
> Subject: RE: [PATCH v1] soc: imx: imx8mp-blk-ctrl: Add PCIe SYSPLL
> configurations
> 
> > -----Original Message-----
> > From: Lucas Stach <l.stach@xxxxxxxxxxxxxx>
> > Sent: 2022年11月1日 16:45
> > To: Shawn Guo <shawnguo@xxxxxxxxxx>; Hongxing Zhu
> > <hongxing.zhu@xxxxxxx>
> > Cc: marex@xxxxxxx; tharvey@xxxxxxxxxxxxx; vkoul@xxxxxxxxxx;
> > bhelgaas@xxxxxxxxxx; lorenzo.pieralisi@xxxxxxx;
> > alexander.stein@xxxxxxxxxxxxxxx; richard.leitner@xxxxxxxxx;
> > devicetree@xxxxxxxxxxxxxxx; linux-pci@xxxxxxxxxxxxxxx;
> > linux-arm-kernel@xxxxxxxxxxxxxxxxxxx; linux-kernel@xxxxxxxxxxxxxxx;
> > kernel@xxxxxxxxxxxxxx; dl-linux-imx <linux-imx@xxxxxxx>
> > Subject: Re: [PATCH v1] soc: imx: imx8mp-blk-ctrl: Add PCIe SYSPLL
> > configurations
> >
> > Hi Shawn, Richard,
> >
> > Am Samstag, dem 29.10.2022 um 16:45 +0800 schrieb Shawn Guo:
> > > On Mon, Oct 24, 2022 at 01:43:09PM +0800, Richard Zhu wrote:
> > > > Add PCIe SYSPLL configurations, thus the internal SYSPLL can be
> > > > used as i.MX8MP PCIe reference clock.
> > > >
> > > > The following properties of PHY dts node should be changed accordingly.
> > > >   - Set 'fsl,refclk-pad-mode' as '<IMX8_PCIE_REFCLK_PAD_OUTPUT>'.
> > > >   - Change 'clocks' to '<&clk IMX8MP_CLK_HSIO_ROOT>'.
> > > >
> > > > Signed-off-by: Richard Zhu <hongxing.zhu@xxxxxxx>
> > >
> > > Applied, thanks!
> >
> > Sorry for the late reply, but I'm not really happy with the fact that
> > the PLL is now unconditionally enabled, even though it is only needed
> > when there is no external reference clock source.
> > I fear that this will be hard to correct later on as the DT
> > abstraction is wrong, as IMX8MP_CLK_HSIO_ROOT is NOT the reference
> > clock for the PHY, but the PLL generated clock, which isn't properly exposed
> with this series.
> Hi Lucas:
> First of all, thanks for your comments.
> 
> IMHO, I'm not sure it's proper or not to describe the hardware logic in  the
> PHY node when internal SYSPLL is used as PCIe PHY reference clock.
> So, I'm trying to get some suggestions and used to send out an email to  you
> and Marcel on Sep20.
> 
> Okay, if you think it's not correct to expose IMX8MP_CLK_HSIO_ROOT clock
> out.
> Which clock you are prefer to use as PHY reference clock here?
> 
> Thanks.
> 
> Best Regards
> Richard Zhu
> >
> > I'm not happy to see this going in in the current state and if not too
> > late would like to ask Shawn to remove it from the tree again.
Hi Lucas:
Refer to the "Reference Clock Section" of i.MX8MP PCIe PHY document.
I_pll_refclk_from_syspll clock is used as reference clock when Inner chip
 clock mode is used.

In the current codes, IMX8MP_CLK_HSIO_AXI is source from sys_pll2 clock.
is it reasonable that use it as PCIe reference clock in this scenario here?

Best Regards
Richard Zhu

> >
> > Regards,
> > Lucas