RE: [PATCH v3 1/8] ACPI: CPPC: Add AMD pstate energy performance preference cppc control

[Yuan, Perry]

[AMD Official Use Only - General]

Hi Rafael. 

> -----Original Message-----
> From: Rafael J. Wysocki <rafael@xxxxxxxxxx>
> Sent: Thursday, November 10, 2022 11:56 PM
> To: Yuan, Perry <Perry.Yuan@xxxxxxx>
> Cc: Rafael J. Wysocki <rafael@xxxxxxxxxx>; Limonciello, Mario
> <Mario.Limonciello@xxxxxxx>; rafael.j.wysocki@xxxxxxxxx; Huang, Ray
> <Ray.Huang@xxxxxxx>; viresh.kumar@xxxxxxxxxx; Sharma, Deepak
> <Deepak.Sharma@xxxxxxx>; Fontenot, Nathan
> <Nathan.Fontenot@xxxxxxx>; Deucher, Alexander
> <Alexander.Deucher@xxxxxxx>; Huang, Shimmer
> <Shimmer.Huang@xxxxxxx>; Du, Xiaojian <Xiaojian.Du@xxxxxxx>; Meng,
> Li (Jassmine) <Li.Meng@xxxxxxx>; linux-pm@xxxxxxxxxxxxxxx; linux-
> kernel@xxxxxxxxxxxxxxx
> Subject: Re: [PATCH v3 1/8] ACPI: CPPC: Add AMD pstate energy
> performance preference cppc control
> 
> Caution: This message originated from an External Source. Use proper
> caution when opening attachments, clicking links, or responding.
> 
> 
> On Thu, Nov 10, 2022 at 4:52 PM Yuan, Perry <Perry.Yuan@xxxxxxx> wrote:
> >
> > [AMD Official Use Only - General]
> >
> >
> >
> > > -----Original Message-----
> > > From: Rafael J. Wysocki <rafael@xxxxxxxxxx>
> > > Sent: Thursday, November 10, 2022 10:50 PM
> > > To: Limonciello, Mario <Mario.Limonciello@xxxxxxx>; Yuan, Perry
> > > <Perry.Yuan@xxxxxxx>
> > > Cc: rafael.j.wysocki@xxxxxxxxx; Huang, Ray <Ray.Huang@xxxxxxx>;
> > > viresh.kumar@xxxxxxxxxx; Sharma, Deepak <Deepak.Sharma@xxxxxxx>;
> > > Fontenot, Nathan <Nathan.Fontenot@xxxxxxx>; Deucher, Alexander
> > > <Alexander.Deucher@xxxxxxx>; Huang, Shimmer
> <Shimmer.Huang@xxxxxxx>;
> > > Du, Xiaojian <Xiaojian.Du@xxxxxxx>; Meng, Li (Jassmine)
> > > <Li.Meng@xxxxxxx>; linux-pm@xxxxxxxxxxxxxxx; linux-
> > > kernel@xxxxxxxxxxxxxxx
> > > Subject: Re: [PATCH v3 1/8] ACPI: CPPC: Add AMD pstate energy
> > > performance preference cppc control
> > >
> > > Caution: This message originated from an External Source. Use proper
> > > caution when opening attachments, clicking links, or responding.
> > >
> > >
> > > On Mon, Nov 7, 2022 at 7:44 PM Limonciello, Mario
> > > <mario.limonciello@xxxxxxx> wrote:
> > > >
> > > > On 11/7/2022 11:56, Perry Yuan wrote:
> > > > > Add the EPP(Energy Performance Preference) support for the AMD
> > > > > SoCs without the dedicated CPPC MSR, those SoCs need to add this
> > > > > cppc acpi functions to update EPP values and desired perf value.
> > > >
> > > > As far as I can tell this is generic code.  Although the reason
> > > > you're submitting it is for enabling AMD SoCs, the commit message
> > > > should be worded as such.
> > > >
> > > > >
> > > > > In order to get EPP worked, cppc_get_epp_caps() will query EPP
> > > > > preference value and cppc_set_epp_perf() will set EPP new value.
> > > > > Before the EPP works, pstate driver will use cppc_set_auto_epp()
> > > > > to enable EPP function from firmware firstly.
> > > >
> > > > This could more succinctly say:
> > > >
> > > > "Add support for setting and querying EPP preferences to the
> > > > generic CPPC driver.  This enables downstream drivers such as
> > > > amd-pstate to discover and use these values."
> > > >
> > > > >
> > > > > Signed-off-by: Perry Yuan <Perry.Yuan@xxxxxxx>
> > > > > ---
> > > > >   drivers/acpi/cppc_acpi.c | 126
> > > +++++++++++++++++++++++++++++++++++++++
> > > > >   include/acpi/cppc_acpi.h |  17 ++++++
> > > > >   2 files changed, 143 insertions(+)
> > > > >
> > > > > diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c
> > > > > index 093675b1a1ff..d9c38dee1f48 100644
> > > > > --- a/drivers/acpi/cppc_acpi.c
> > > > > +++ b/drivers/acpi/cppc_acpi.c
> > > > > @@ -1365,6 +1365,132 @@ int cppc_get_perf_ctrs(int cpunum,
> > > > > struct
> > > cppc_perf_fb_ctrs *perf_fb_ctrs)
> > > > >   }
> > > > >   EXPORT_SYMBOL_GPL(cppc_get_perf_ctrs);
> > > > >
> > > > > +/**
> > > > > + * cppc_get_epp_caps - Get the energy preference register value.
> > > > > + * @cpunum: CPU from which to get epp preference level.
> > > > > + * @perf_caps: Return address.
> > > > > + *
> > > > > + * Return: 0 for success, -EIO otherwise.
> > > > > + */
> > > > > +int cppc_get_epp_caps(int cpunum, struct cppc_perf_caps
> > > > > +*perf_caps) {
> > > > > +     struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum);
> > > > > +     struct cpc_register_resource *energy_perf_reg;
> > > > > +     u64 energy_perf;
> > > > > +
> > > > > +     if (!cpc_desc) {
> > > > > +             pr_warn("No CPC descriptor for CPU:%d\n", cpunum);
> > > > > +             return -ENODEV;
> > > > > +     }
> > > > > +
> > > > > +     energy_perf_reg = &cpc_desc->cpc_regs[ENERGY_PERF];
> > > > > +
> > > > > +     if (!CPC_SUPPORTED(energy_perf_reg))
> > > > > +             pr_warn("energy perf reg update is
> > > > > + unsupported!\n");
> > > >
> > > > No need to add a explanation point at the end.
> > > >
> > > > As this is a per-CPU message I wonder if this would be better as
> > > > pr_warn_once()?  Othewrise some systems with large numbers of
> > > > cores might potentially show this message quite a few times.
> > >
> > > pr_info_once() would suffice IMO.
> >
> > Fixed in V4.
> >
> > >
> > > > > +
> > > > > +     if (CPC_IN_PCC(energy_perf_reg)) {
> > > > > +             int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpunum);
> > > > > +             struct cppc_pcc_data *pcc_ss_data = NULL;
> > > > > +             int ret = 0;
> > > > > +
> > > > > +             if (pcc_ss_id < 0)
> > > > > +                     return -ENODEV;
> > > > > +
> > > > > +             pcc_ss_data = pcc_data[pcc_ss_id];
> > > > > +
> > > > > +             down_write(&pcc_ss_data->pcc_lock);
> > > > > +
> > > > > +             if (send_pcc_cmd(pcc_ss_id, CMD_READ) >= 0) {
> > > > > +                     cpc_read(cpunum, energy_perf_reg, &energy_perf);
> > > > > +                     perf_caps->energy_perf = energy_perf;
> > > > > +             } else {
> > > > > +                     ret = -EIO;
> > > > > +             }
> > > > > +
> > > > > +             up_write(&pcc_ss_data->pcc_lock);
> > > > > +
> > > > > +             return ret;
> > > > > +     }
> > >
> > > What if CPC is not in PCC?
> > >
> > > Would returning 0 then work for all users?
> >
> > Fixed in V4
> >
> > >
> > > > > +
> > > > > +     return 0;
> > > > > +}
> > > > > +EXPORT_SYMBOL_GPL(cppc_get_epp_caps);
> > > > > +
> > > > > +int cppc_set_auto_epp(int cpu, bool enable) {
> > > > > +     int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
> > > > > +     struct cpc_register_resource *auto_sel_reg;
> > > > > +     struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu);
> > > > > +     struct cppc_pcc_data *pcc_ss_data = NULL;
> > > > > +     int ret = -EINVAL;
> > > > > +
> > > > > +     if (!cpc_desc) {
> > > > > +             pr_warn("No CPC descriptor for CPU:%d\n", cpu);
> > > >
> > > > Is this actually warn worthy?  I would think it's fine a debug
> > > > like we have for the other _CPC missing messages.
> > > >
> > > > > +             return -EINVAL;
> > > > > +     }
> > > > > +
> > > > > +     auto_sel_reg = &cpc_desc->cpc_regs[AUTO_SEL_ENABLE];
> > > > > +
> > > > > +     if (CPC_IN_PCC(auto_sel_reg)) {
> > > > > +             if (pcc_ss_id < 0)
> > > > > +                     return -ENODEV;
> > > > > +
> > > > > +             ret = cpc_write(cpu, auto_sel_reg, enable);
> > > > > +             if (ret)
> > > > > +                     return ret;
> > > > > +
> > > > > +             pcc_ss_data = pcc_data[pcc_ss_id];
> > > > > +
> > > > > +             down_write(&pcc_ss_data->pcc_lock);
> > > > > +             /* after writing CPC, transfer the ownership of PCC to
> platform */
> > > > > +             ret = send_pcc_cmd(pcc_ss_id, CMD_WRITE);
> > > > > +             up_write(&pcc_ss_data->pcc_lock);
> > > > > +             return ret;
> > > > > +     }
> > > > > +
> > > > > +     return cpc_write(cpu, auto_sel_reg, enable); }
> > > > > +EXPORT_SYMBOL_GPL(cppc_set_auto_epp);
> > > > > +
> > > > > +/*
> > > > > + * Set Energy Performance Preference Register value through
> > > > > + * Performance Controls Interface  */ int cppc_set_epp_perf(int
> > > > > +cpu, struct cppc_perf_ctrls *perf_ctrls) {
> > > > > +     int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
> > > > > +     struct cpc_register_resource *epp_set_reg;
> > > > > +     struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu);
> > > > > +     struct cppc_pcc_data *pcc_ss_data = NULL;
> > > > > +     int ret = -EINVAL;
> > > > > +
> > > > > +     if (!cpc_desc) {
> > > > > +             pr_warn("No CPC descriptor for CPU:%d\n", cpu);
> > > >
> > > > Is this actually warn worthy?  I would think it's fine a debug
> > > > like we have for the other _CPC missing messages.
> > > >
> > > > > +             return -EINVAL;
> > > > > +     }
> > > > > +
> > > > > +     epp_set_reg = &cpc_desc->cpc_regs[ENERGY_PERF];
> > > > > +
> > > > > +     if (CPC_IN_PCC(epp_set_reg)) {
> > > > > +             if (pcc_ss_id < 0)
> > > > > +                     return -ENODEV;
> > > > > +
> > > > > +             ret = cpc_write(cpu, epp_set_reg, perf_ctrls->energy_perf);
> > > > > +             if (ret)
> > > > > +                     return ret;
> > > > > +
> > > > > +             pcc_ss_data = pcc_data[pcc_ss_id];
> > > > > +
> > > > > +             down_write(&pcc_ss_data->pcc_lock);
> > > > > +             /* after writing CPC, transfer the ownership of PCC to
> platform */
> > > > > +             ret = send_pcc_cmd(pcc_ss_id, CMD_WRITE);
> > > > > +             up_write(&pcc_ss_data->pcc_lock);
> > > >
> > > > cppc_set_auto_epp and cppc_set_epp_perf have nearly the same
> code
> > > > in the if block.  I wonder if it's worth having a static helper
> > > > function for this purpose that takes "reg" and "value" as arguments?
> > > >
> > > > > +     }
> > >
> > > And what about the non-PCC case here?
> >
> > I merge the  cppc_set_auto_epp and cppc_set_epp_perf in V4.
> > For the non-PCC case, we canno set the EPP value to FW, then just
> > returned Error code.  Is it Ok ?
> 
> Yes, if it cannot be updated, it should be treated the same way as
> unsupported IMV.

Make sense, I will make change for this in V4 and you can help to take a look at V4.
Thanks. 

Perry .