Re: [PATCH 1/2] cxl/pci: Add generic MSI-X/MSI irq support
From: Ira Weiny
Date: Wed Nov 09 2022 - 22:31:21 EST
On Thu, Nov 03, 2022 at 06:09:16PM +0000, Jonathan Cameron wrote:
> On Wed, 2 Nov 2022 17:18:33 -0700
> Davidlohr Bueso <dave@xxxxxxxxxxxx> wrote:
>
> > On Wed, 02 Nov 2022, Ira Weiny wrote:
> >
> > >On Wed, Nov 02, 2022 at 10:15:24AM -0700, Davidlohr Bueso wrote:
> > >> Most CXL features that can have irqs will normally use only the first 16,
> > >> with the exception of isolation (cxl 3.0), which per the spec is up to 32.
> > >
> > >Dan, Dave, and I were discussing this and we agree. For now the only things
> > >people are working on are within the first 16 so why not just request 16 as the
> > >max for now?
> >
> > It is a fair compromise, yes.
>
> works for me.
I made what I thought would be a simple change to your patch and built this
into my series.
Unfortunately the following does not work with the current Qemu.
/*
* NOTE: Currently all the functions which are enabled for CXL require their
* vectors to be in the first 16. Allocate this number as the min/max.
*/
#define CXL_PCI_REQUIRED_VECTORS 16
...
rc = pci_alloc_irq_vectors(pdev, CXL_PCI_REQUIRED_VECTORS,
CXL_PCI_REQUIRED_VECTORS,
PCI_IRQ_MSIX | PCI_IRQ_MSI);
This is because Qemu CXL devices only support (with the event changes I have
made) 8 msg numbers. So the code fails to allocate any vectors.
I guess I should have known better. But allocating something less than 16 I
guess needs to be allowed.
But that also means that beyond knowing _if_ irq's have been enabled I think
each CXL feature needs to know the number of vectors allocated so they can
ensure their msg numbers are going to work.
So how about the following as a diff to this patch?
In the event code I have then used the nr_irq_vecs field to determine if I
should enable the irq for each log.
If you are ok with it I'm going to squash it into your patch and send out a new
version of the event log series.
Thanks,
Ira