RE: [PATCH v5 2/2] dt-bindings: PCI: xilinx-nwl: Convert to YAML schemas of Xilinx NWL PCIe Root Port Bridge

[Havalige, Thippeswamy]

Hi,

> > +  dma-coherent:
> > +    description: Optional, present if DMA operations are coherent
> > +
> > +  clocks:
> > +    description: Optional, input clock specifier.
> 
> This is a friendly reminder during the review process.
> 
> It seems my previous comments were not fully addressed. Maybe my
> feedback got lost between the quotes, maybe you just forgot to apply it.
> Please go back to the previous discussion and either implement all requested
> changes or keep discussing them.
> 
> Hint: same comment as v3.

Sorry I assumed it only for 'Input' and not Optional.

Regards,
Thippeswamy H