Re: [PATCH 2/3] x86/cpu/amd: Add feature bit for MSR_AMD64_LS_CFG enumeration

[Pawan Gupta]

On Tue, Nov 08, 2022 at 07:54:01PM +0100, Borislav Petkov wrote:
> On Mon, Sep 12, 2022 at 04:40:47PM -0700, Pawan Gupta wrote:
> > Currently there is no easy way to enumerate MSR_AMD64_LS_CFG. As this
> > MSR is supported on AMD CPU families 10h to 18h, set a new feature bit
> > on these CPU families. The new bit can be used to detect the MSR
> > support.
> >
> > Suggested-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
> > Signed-off-by: Pawan Gupta <pawan.kumar.gupta@xxxxxxxxxxxxxxx>
> > ---
> >  arch/x86/include/asm/cpufeatures.h | 1 +
> >  arch/x86/kernel/cpu/amd.c          | 3 +++
> >  2 files changed, 4 insertions(+)
> >
> > diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
> > index dd173733e40d..90bdb1d98531 100644
> > --- a/arch/x86/include/asm/cpufeatures.h
> > +++ b/arch/x86/include/asm/cpufeatures.h
> > @@ -305,6 +305,7 @@
> >  #define X86_FEATURE_USE_IBPB_FW		(11*32+16) /* "" Use IBPB during runtime firmware calls */
> >  #define X86_FEATURE_RSB_VMEXIT_LITE	(11*32+17) /* "" Fill RSB on VM exit when EIBRS is enabled */
> >  #define X86_FEATURE_MSR_TSX_CTRL	(11*32+18) /* "" MSR IA32_TSX_CTRL */
> > +#define X86_FEATURE_MSR_LS_CFG		(11*32+19) /* "" MSR AMD64_LS_CFG */
>
> We already have that one:
>
> #define X86_FEATURE_LS_CFG_SSBD         ( 7*32+24)  /* "" AMD SSBD implementation via LS_CFG MSR */

Looking at bsp_init_amd() this feature bit will only be set on AMD
families 0x15-0x17. Andrew mentioned that the MSR LS_CFG is present on
AMD family >= 0x10 && family <= 0x18. That is why I added a new bit for
the MSR.