Re: [PATCH 2/2] soc: qcom: spm: Implement support for SAWv2.3, MSM8976 L2 PM

[Konrad Dybcio]

On 04/11/2022 14:34, AngeloGioacchino Del Regno wrote:
> From: AngeloGioacchino Del Regno <angelogioacchino.delregno@xxxxxxxxxxxxxx>
>
> Implement the support for SAW v2.3, used in at least MSM8976, MSM8956
> and APQ variants and while at it also add the configuration for the
> MSM8976's little (a53) and big (a72) clusters cache power management.
>
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@xxxxxxxxxxxxxx>
> [Marijn: reorder struct definitions to follow high-to-low order]

Weird to have a name without an email address in any of the tags, but I

suppose it's not much of an issue?


> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@xxxxxxxxxxxxx>
> ---

For the code:

Reviewed-by: Konrad Dybcio <konrad.dybcio@xxxxxxxxxxxxxx>


Konrad

>   drivers/soc/qcom/spm.c | 33 +++++++++++++++++++++++++++++++++
>   1 file changed, 33 insertions(+)
>
> diff --git a/drivers/soc/qcom/spm.c b/drivers/soc/qcom/spm.c
> index 484b42b7454e..bfcd321d7837 100644
> --- a/drivers/soc/qcom/spm.c
> +++ b/drivers/soc/qcom/spm.c
> @@ -98,6 +98,35 @@ static const struct spm_reg_data spm_reg_8916_cpu = {
>   	.start_index[PM_SLEEP_MODE_SPC] = 5,
>   };
>   
> +static const u16 spm_reg_offset_v2_3[SPM_REG_NR] = {
> +	[SPM_REG_CFG]		= 0x08,
> +	[SPM_REG_SPM_CTL]	= 0x30,
> +	[SPM_REG_DLY]		= 0x34,
> +	[SPM_REG_PMIC_DATA_0]	= 0x40,
> +	[SPM_REG_PMIC_DATA_1]	= 0x44,
> +};
> +
> +/* SPM register data for 8976 */
> +static const struct spm_reg_data spm_reg_8976_gold_l2 = {
> +	.reg_offset = spm_reg_offset_v2_3,
> +	.spm_cfg = 0x14,
> +	.spm_dly = 0x3c11840a,
> +	.pmic_data[0] = 0x03030080,
> +	.pmic_data[1] = 0x00030000,
> +	.start_index[PM_SLEEP_MODE_STBY] = 0,
> +	.start_index[PM_SLEEP_MODE_SPC] = 3,
> +};
> +
> +static const struct spm_reg_data spm_reg_8976_silver_l2 = {
> +	.reg_offset = spm_reg_offset_v2_3,
> +	.spm_cfg = 0x14,
> +	.spm_dly = 0x3c102800,
> +	.pmic_data[0] = 0x03030080,
> +	.pmic_data[1] = 0x00030000,
> +	.start_index[PM_SLEEP_MODE_STBY] = 0,
> +	.start_index[PM_SLEEP_MODE_SPC] = 2,
> +};
> +
>   static const u16 spm_reg_offset_v2_1[SPM_REG_NR] = {
>   	[SPM_REG_CFG]		= 0x08,
>   	[SPM_REG_SPM_CTL]	= 0x30,
> @@ -213,6 +242,10 @@ static const struct of_device_id spm_match_table[] = {
>   	  .data = &spm_reg_8916_cpu },
>   	{ .compatible = "qcom,msm8974-saw2-v2.1-cpu",
>   	  .data = &spm_reg_8974_8084_cpu },
> +	{ .compatible = "qcom,msm8976-gold-saw2-v2.3-l2",
> +	  .data = &spm_reg_8976_gold_l2 },
> +	{ .compatible = "qcom,msm8976-silver-saw2-v2.3-l2",
> +	  .data = &spm_reg_8976_silver_l2 },
>   	{ .compatible = "qcom,msm8998-gold-saw2-v4.1-l2",
>   	  .data = &spm_reg_8998_gold_l2 },
>   	{ .compatible = "qcom,msm8998-silver-saw2-v4.1-l2",