RE: [PATCH v2 tty-next 1/3] 8250: microchip: pci1xxxx: Add driver for quad-uart support.

[Kumaravel.Thiagarajan]

> -----Original Message-----
> From: Andy Shevchenko <andy.shevchenko@xxxxxxxxx>
> Sent: Tuesday, November 1, 2022 8:47 PM
> To: Tharunkumar Pasumarthi - I67821
> <Tharunkumar.Pasumarthi@xxxxxxxxxxxxx>
> Subject: Re: [PATCH v2 tty-next 1/3] 8250: microchip: pci1xxxx: Add driver for
> quad-uart support.
>  
> On Tue, Nov 1, 2022 at 5:04 PM <Tharunkumar.Pasumarthi@xxxxxxxxxxxxx>
> wrote:
> > > From: Andy Shevchenko <andy.shevchenko@xxxxxxxxx>
> > > Sent: Monday, October 31, 2022 8:07 PM
> 
> ...
> 
> > > > But, if I do this, I cannot use sysfs interface for updating rx_trig_bytes
> right?
> > >
> > > Maybe, I don't remember by heart that part of the code. But why do
> > > you need that ABI in the first place?
> >
> > By using the sysfs interface, our driver will be able to update the trigger
> level for the receiver fifo interrupt at runtime.
> 
> This doesn't answer my question. What is this needed for?
I think this will be useful for our customers in tuning the trigger level based on their application.
This is a UART based on programmed I/O and at higher speeds sometimes where there can be
continuous stream of data for a long time, we may need to set the trigger to the lower side to detect
early and avoid overflow.
On the other hand, in some applications where the continuous stream of data is not very long and
no risk of overflow, set it to higher side to avoid frequent interrupts..
We just want to keep this option open in the driver for different customers who would want to tune
this based on their application.
Please let us know if there are further questions or any issues in this approach.

Thank You.

Regards,
Kumar