[PATCH V2 12/15] arm64: dts: imx8mn-evk: enable usdhc1

From: Peng Fan (OSS)
Date: Sun Oct 23 2022 - 23:15:52 EST


From: Peng Fan <peng.fan@xxxxxxx>

Enable usdhc1 for wlan usage, the wifi device node not included.

Signed-off-by: Peng Fan <peng.fan@xxxxxxx>
---
arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi | 69 +++++++++++++++++++
1 file changed, 69 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi
index f137eb406c24..50553359401f 100644
--- a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi
@@ -28,6 +28,13 @@ memory@40000000 {
reg = <0x0 0x40000000 0 0x80000000>;
};

+ usdhc1_pwrseq: usdhc1_pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc1_gpio>;
+ reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
+ };
+
reg_usdhc2_vmmc: regulator-usdhc2 {
compatible = "regulator-fixed";
pinctrl-names = "default";
@@ -271,6 +278,22 @@ &uart3 {
status = "okay";
};

+&usdhc1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_wlan>;
+ pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_wlan>;
+ pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_wlan>;
+ bus-width = <4>;
+ keep-power-in-suspend;
+ non-removable;
+ wakeup-source;
+ fsl,sdio-async-interrupt-enabled;
+ mmc-pwrseq = <&usdhc1_pwrseq>;
+ status = "okay";
+};
+
&usbotg1 {
dr_mode = "otg";
hnp-disable;
@@ -474,6 +497,45 @@ MX8MN_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x140
>;
};

+ pinctrl_usdhc1_gpio: usdhc1grpgpio {
+ fsl,pins = <
+ MX8MN_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
+ MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
+ MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
+ MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
+ MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
+ MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
+ >;
+ };
+
+ pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
+ fsl,pins = <
+ MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x194
+ MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4
+ MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4
+ MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4
+ MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4
+ MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4
+ >;
+ };
+
+ pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
+ fsl,pins = <
+ MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x196
+ MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6
+ MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6
+ MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6
+ MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6
+ MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6
+ >;
+ };
+
pinctrl_usdhc2_gpio: usdhc2gpiogrp {
fsl,pins = <
MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4
@@ -569,4 +631,11 @@ pinctrl_wdog: wdoggrp {
MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166
>;
};
+
+ pinctrl_wlan: wlangrp {
+ fsl,pins = <
+ MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x141
+ MX8MN_IOMUXC_SD1_DATA7_GPIO2_IO9 0x159
+ >;
+ };
};
--
2.37.1