Re: [PATCH v2 11/11] phy: qcom-qmp-pcie: drop bogus register update

[Dmitry Baryshkov]

On Thu, 29 Sept 2022 at 12:29, Johan Hovold <johan+linaro@xxxxxxxxxx> wrote:
>
> Since commit 0d58280cf1e6 ("phy: Update PHY power control sequence") the
> PHY is powered on before configuring the registers and only the MSM8996
> PCIe PHY, which includes the POWER_DOWN_CONTROL register in its PCS
> initialisation table, may possibly require a second update afterwards.
>
> To make things worse, the POWER_DOWN_CONTROL register lies at a
> different offset on more recent SoCs so that the second update, which
> still used a hard-coded offset, would write to an unrelated register
> (e.g. a revision-id register on SC8280XP).
>
> As the MSM8996 PCIe PHY is now handled by a separate driver, simply drop
> the bogus register update.
>
> Fixes: e4d8b05ad5f9 ("phy: qcom-qmp: Use proper PWRDOWN offset for sm8150 USB") added support

Unless somebody confirms that this write is not needed on 8998 and
sdm845, I'd prefer a two stage fix here:
- changing this to write to proper register (and maybe moving to the
top of patch series, as we'd want to backport this to the last few
kernels)
- dropping the write completely.

Meanwhile I'll try testing this patchset on rb3 and checking whether
it makes any difference or not.

> Signed-off-by: Johan Hovold <johan+linaro@xxxxxxxxxx>
> ---
>  drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 6 ------
>  1 file changed, 6 deletions(-)
>
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
> index a0f62e9633d9..90bdbeee8372 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
> @@ -1963,12 +1963,6 @@ static int qmp_pcie_power_on(struct phy *phy)
>         qmp_pcie_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl, cfg->pcs_misc_tbl_num);
>         qmp_pcie_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl_sec, cfg->pcs_misc_tbl_num_sec);
>
> -       /*
> -        * Pull out PHY from POWER DOWN state.
> -        * This is active low enable signal to power-down PHY.
> -        */
> -       qphy_setbits(pcs, QPHY_V2_PCS_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl);
> -
>         if (cfg->has_pwrdn_delay)
>                 usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max);
>
> --
> 2.35.1
>


-- 
With best wishes
Dmitry